8d313685b0
in device trees. Adapt sconfig as necessary. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
64 lines
2.1 KiB
Text
64 lines
2.1 KiB
Text
chip northbridge/via/cn700 # Northbridge
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device pci_domain 0 on # PCI domain
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device pci 0.0 on end # AGP Bridge
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device pci 0.1 on end # Error Reporting
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device pci 0.2 on end # Host Bus Control
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device pci 0.3 on end # Memory Controller
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device pci 0.4 on end # Power Management
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device pci 0.7 on end # V-Link Controller
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device pci 1.0 on end # PCI Bridge
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chip southbridge/via/vt8237r # Southbridge
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# Enable both IDE channels.
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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# Both cables are 40pin.
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register "ide0_80pin_cable" = "0"
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register "ide1_80pin_cable" = "0"
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register "fn_ctrl_lo" = "0x80"
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register "fn_ctrl_hi" = "0x1d"
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device pci f.0 on end # IDE
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device pci 10.0 on end # UHCI
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device pci 10.1 on end # UHCI
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device pci 10.2 on end # UHCI
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device pci 10.3 on end # UHCI
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device pci 10.4 on end # EHCI
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device pci 11.0 on # Southbridge LPC
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chip superio/winbond/w83697hf # Super I/O
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 on # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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drq 0x74 = 3
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end
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device pnp 2e.2 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on # COM2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.6 off end # Consumer IR
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device pnp 2e.7 off end # Game port, GPIO 1
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device pnp 2e.8 off end # MIDI port, GPIO 5
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device pnp 2e.9 off end # GPIO 2-4
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device pnp 2e.a off end # ACPI
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device pnp 2e.b on # HWM
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io 0x60 = 0x290
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end
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end
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end
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device pci 11.5 on end # AC'97 audio
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device pci 12.0 on end # Ethernet
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end
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end
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device lapic_cluster 0 on # APIC cluster
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chip cpu/via/model_c7 # VIA C7
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device lapic 0 on end # APIC
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end
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end
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end
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