Kyösti Mälkki 0e1ea279d0 AGESA vendorcode: Add ENABLE_MRC_CACHE option ... When selected, try to store and restore memory training results from/to SPI flash. This change only pulls in the required parts from vendorcode for the build. Change-Id: I12880237be494c71e1d4836abd2d4b714ba87762 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2017-10-05 13:23:27 +00:00
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amd	AGESA vendorcode: Add ENABLE_MRC_CACHE option	2017-10-05 13:23:27 +00:00
google	Rename __attribute__((packed)) --> __packed	2017-07-13 19:45:59 +00:00
intel	intel/fsp: Update cannonlake FSP header	2017-10-04 02:55:29 +00:00
siemens	vendorcode/siemens: Add LegacyDelay to hwilib	2017-09-13 16:22:26 +00:00
Makefile.inc	vendorcode/siemens: Add hwilib for Siemens specific info struct	2016-04-28 08:15:47 +02:00