efa606b77b
Add LPC common code to be shared across Intel platforms.
Also add LPC library functions to be shared across platforms.
Use common LPC code for Apollo Lake soc. Update existing Apollolake
mainboard variants {google,intel,siemens} to use new common
LPC header file.
Change-Id: I6ac2e9c195b9ecda97415890cc615f4efb04a27a
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/20659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
162 lines
4.8 KiB
Makefile
162 lines
4.8 KiB
Makefile
ifeq ($(CONFIG_SOC_INTEL_APOLLOLAKE),y)
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subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/intel/turbo
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subdirs-y += ../../../cpu/x86/lapic
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subdirs-y += ../../../cpu/x86/mtrr
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subdirs-y += ../../../cpu/x86/smm
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subdirs-y += ../../../cpu/x86/tsc
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subdirs-y += ../../../cpu/x86/cache
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bootblock-y += bootblock/bootblock.c
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bootblock-y += car.c
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bootblock-y += heci.c
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bootblock-y += i2c.c
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bootblock-y += lpc.c
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bootblock-y += mmap_boot.c
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bootblock-y += pmutil.c
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bootblock-y += spi.c
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bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S
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romstage-y += car.c
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romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
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romstage-y += heci.c
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romstage-y += i2c.c
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romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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romstage-y += memmap.c
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romstage-y += meminit.c
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ifeq ($(CONFIG_SOC_INTEL_GLK),y)
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romstage-y += meminit_util_glk.c
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else
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romstage-y += meminit_util_apl.c
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endif
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romstage-y += mmap_boot.c
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romstage-y += pmutil.c
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romstage-y += reset.c
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romstage-y += spi.c
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smm-y += mmap_boot.c
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smm-y += pmutil.c
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smm-y += smihandler.c
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smm-y += spi.c
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smm-y += uart_early.c
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smm-y += uart.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
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ramstage-y += cpu.c
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ramstage-y += chip.c
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ramstage-y += cse.c
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ramstage-y += elog.c
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ramstage-y += dsp.c
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ramstage-y += graphics.c
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ramstage-y += heci.c
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ramstage-y += i2c.c
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ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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ramstage-y += lpc.c
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ramstage-y += memmap.c
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ramstage-y += mmap_boot.c
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ramstage-y += p2sb.c
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ramstage-y += uart.c
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ramstage-y += nhlt.c
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ramstage-y += systemagent.c
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ramstage-y += spi.c
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ramstage-y += pmutil.c
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ramstage-y += pmc.c
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ramstage-y += reset.c
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ramstage-y += sram.c
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ramstage-y += spi.c
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ramstage-y += xdci.c
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ramstage-y += sd.c
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postcar-y += memmap.c
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postcar-y += mmap_boot.c
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postcar-y += spi.c
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postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S
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verstage-y += car.c
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verstage-y += i2c.c
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verstage-y += heci.c
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verstage-y += memmap.c
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verstage-y += mmap_boot.c
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verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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verstage-y += pmutil.c
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verstage-y += reset.c
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verstage-y += spi.c
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ifeq ($(CONFIG_SOC_INTEL_GLK),y)
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bootblock-y += gpio_glk.c
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romstage-y += gpio_glk.c
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smm-y += gpio_glk.c
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ramstage-y += gpio_glk.c
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else
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bootblock-y += gpio_apl.c
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romstage-y += gpio_apl.c
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smm-y += gpio_apl.c
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ramstage-y += gpio_apl.c
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endif
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CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
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ifeq ($(CONFIG_SOC_INTEL_GLK),y)
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CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/glk
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else
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CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/apollolake
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endif
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# Since FSP-M runs in CAR we need to relocate it to a specific address
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$(CONFIG_FSP_M_CBFS)-options := -b $(CONFIG_FSP_M_ADDR)
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ifeq ($(CONFIG_NEED_LBP2),y)
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files_added::
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$(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_LBP2_FMAP_NAME) -f $(CONFIG_LBP2_FILE_NAME) --fill-upward
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endif
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# Bootblock on Apollolake platform lies in the IFWI region. In order to place
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# the bootblock at the right location in IFWI image -
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# a. Using ifwitool:
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# 1. Create IFWI image (ifwi.bin.tmp) from input image
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# (CONFIG_IFWI_FILE_NAME).
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# 2. Delete OBBP sub-partition, if present.
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# 3. Replace IBBL directory entry in IBBP sub-partition with currently
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# generated bootblock.bin.
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# b. Using cbfstool:
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# 1. Write ifwi.bin.tmp to coreboot.rom using CONFIG_IFWI_FMAP_NAME.
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ifeq ($(CONFIG_NEED_IFWI),y)
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files_added:: $(IFWITOOL)
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$(IFWITOOL) $(CONFIG_IFWI_FILE_NAME) create -f $(objcbfs)/ifwi.bin.tmp
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$(IFWITOOL) $(objcbfs)/ifwi.bin.tmp delete -n OBBP
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$(IFWITOOL) $(objcbfs)/ifwi.bin.tmp replace -n IBBP -f $(objcbfs)/bootblock.bin -d -e IBBL
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$(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_IFWI_FMAP_NAME) -f $(objcbfs)/ifwi.bin.tmp --fill-upward
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endif
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# DSP firmware settings files.
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NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/apollolake/nhlt-blobs
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DMIC_1CH_48KHZ_16B = dmic-1ch-48khz-16b.bin
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DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin
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DMIC_4CH_48KHZ_16B = dmic-4ch-48khz-16b.bin
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MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin
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DA7219_RENDER_CAPTURE = dialog-2ch-48khz-24b.bin
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cbfs-files-$(CONFIG_NHLT_DMIC_1CH_16B) += $(DMIC_1CH_48KHZ_16B)
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$(DMIC_1CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_1CH_48KHZ_16B)
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$(DMIC_1CH_48KHZ_16B)-type := raw
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cbfs-files-$(CONFIG_NHLT_DMIC_2CH_16B) += $(DMIC_2CH_48KHZ_16B)
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$(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B)
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$(DMIC_2CH_48KHZ_16B)-type := raw
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cbfs-files-$(CONFIG_NHLT_DMIC_4CH_16B) += $(DMIC_4CH_48KHZ_16B)
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$(DMIC_4CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_4CH_48KHZ_16B)
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$(DMIC_4CH_48KHZ_16B)-type := raw
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cbfs-files-$(CONFIG_NHLT_MAX98357) += $(MAX98357_RENDER)
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$(MAX98357_RENDER)-file := $(NHLT_BLOB_PATH)/$(MAX98357_RENDER)
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$(MAX98357_RENDER)-type := raw
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cbfs-files-$(CONFIG_NHLT_DA7219) += $(DA7219_RENDER_CAPTURE)
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$(DA7219_RENDER_CAPTURE)-file := $(NHLT_BLOB_PATH)/$(DA7219_RENDER_CAPTURE)
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$(DA7219_RENDER_CAPTURE)-type := raw
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endif
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