Lijian Zhao 0f5d7b9daf soc/intel/cannonlake: Add back PM TIMER EMULATION ... ACPI PM timer emulation will be added back as default FSP stops TCO count for power saving, which will also stop ACPI PM timer within PCH. CPU PM TIMER EMULATION will help UEFI payload pass, instead of endless loop wait for ACPI PM timer counter to increase. BUG=N/A TEST=Build and boot up fine with whiskey lake rvp board into UEFI shell. Change-Id: Ie069e815e6244c3f85fabf51e186311621d316fd Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28937 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2018-10-26 11:20:00 +00:00
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apollolake	soc/intel: Consolidate FSP CAR setup and teardown code	2018-10-25 09:26:50 +00:00
baytrail	vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic	2018-10-24 09:07:43 +00:00
braswell	vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic	2018-10-24 09:07:43 +00:00
broadwell	vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic	2018-10-24 09:07:43 +00:00
cannonlake	soc/intel/cannonlake: Add back PM TIMER EMULATION	2018-10-26 11:20:00 +00:00
common	soc/intel/cannonlake: Add back PM TIMER EMULATION	2018-10-26 11:20:00 +00:00
denverton_ns	soc/intel: Consolidate FSP CAR setup and teardown code	2018-10-25 09:26:50 +00:00
fsp_baytrail	vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic	2018-10-24 09:07:43 +00:00
fsp_broadwell_de	intel: Use CF9 reset (part 1)	2018-10-22 08:35:25 +00:00
quark	intel: Use CF9 reset (part 2)	2018-10-22 08:35:32 +00:00
skylake	soc/intel/common/block/gpio: Allow GPI to be dual-routed	2018-10-23 14:36:10 +00:00
Kconfig	Kconfig: Add config to insert ucode address in second FIT	2018-07-19 08:07:49 +00:00