Go to file
Duncan Laurie 1010b4aeac acpi_device: Add support for writing ACPI I2C descriptors
Add required definitions to describe an ACPI I2C bus and a method to
write the I2cSerialBus() descriptor to the SSDT.

This will be used by device drivers to describe their I2C resources to
the OS.  The devicetree i2c device can supply the address and 7 or 10
bit mode as well as indicate the GPIO controller device, and the bus
speed can be fixed or configured by the driver.

chip.h:
  struct drivers_i2c_generic_config {
    enum i2c_speed bus_speed;
  };

generic.c:
  void acpi_fill_ssdt_generator(struct device *dev) {
    struct drivers_i2c_generic_config *config = dev->chip_info;
    struct acpi_i2c i2c = {
      .address = dev->path->i2c.device,
      .mode_10bit = dev->path.i2c.mode_10bit,
      .speed = config->bus_speed ? : I2C_SPEED_FAST,
      .resource = acpi_device_path(dev->bus->dev)
    };
    ...
    acpi_device_write_i2c(&i2c);
    ...
  }

devicetree.cb:
  device pci 15.0 on
    chip drivers/i2c/generic
      device i2c 10.0 on end
    end
  end

SSDT.dsl:
  I2cSerialBus (0x10, ControllerInitiated, 400000, AddressingMode7Bit,
                "\\_SB.PCI0.I2C0", 0, ResourceConsumer)

Change-Id: I598401ac81a92c72f19da0271af1e218580a6c49
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14935
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-28 03:47:09 +02:00
3rdparty 3rdparty/blobs: add more Qualcomm stubs 2016-05-10 21:22:28 +02:00
Documentation Documentation/Intel: Update the documentation 2016-05-18 19:47:16 +02:00
payloads arm64: Add stack dump to exception handler 2016-05-24 20:51:28 +02:00
src acpi_device: Add support for writing ACPI I2C descriptors 2016-05-28 03:47:09 +02:00
util cbfstool: Move cbfs_file_get_header to fit.c 2016-05-26 23:51:08 +02:00
.clang-format Provide coreboot coding style formalisation file for clang-format 2015-11-10 00:49:03 +01:00
.gitignore .gitignore: add build and libpayload dirs for nvramcui payload 2016-05-03 04:16:45 +02:00
.gitmodules git modules: rename git submodules to avoid hierarchies 2016-02-11 20:55:55 +01:00
.gitreview
COPYING
MAINTAINERS MAINTAINERS: Add myself for Apollolake SoC, FSP2.0, and Amenia mb 2016-05-26 23:52:57 +02:00
Makefile Makefile: Update payload clean targets 2016-03-09 17:01:56 +01:00
Makefile.inc splash: Put the suffix of splash file to CBFS name 2016-05-26 23:48:02 +02:00
README
toolchain.inc toolchain.inc: test IASL by version string instead of number 2016-03-04 16:36:25 +01:00

README

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * make
 * gcc / g++
   Because Linux distribution compilers tend to use lots of patches. coreboot
   does lots of "unusual" things in its build system, some of which break due
   to those patches, sometimes by gcc aborting, sometimes - and that's worse -
   by generating broken object code.
   Two options: use our toolchain (eg. make crosstools-i386) or enable the
   ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this
   case).
 * iasl (for targets with ACPI support)

Optional:

 * doxygen (for generating/viewing documentation)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig' and 'make nconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.