fd7440d231
The current Braswell FSP 1.1 header in vendorcode/intel, for which there is no publicly available FSP binary, contains silicon init UPDs which are not found in the publicly available header/binary in the FSP Github repo. This prevents new boards from being added which use the public Braswell FSP header/binary. To resolve this, move the UPDs not found in the public header from the soc's chip.c to ramstage.c for the boards which use them. Add a Kconfig option to use the current non-public FSP header and select it for boards which need it (google/cyan variants); set the public FSP option as the default. Use the Kconfig option to set FSP_HEADER_PATH to ensure the correct header is used. Test: build google/cyan and intel/strago using non-public and public FSP header/binaries respectively. Change-Id: I43cf18b98c844175a87b61fdbe4b0b24484e5702 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
152 lines
3.5 KiB
Text
152 lines
3.5 KiB
Text
config SOC_INTEL_BRASWELL
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bool
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help
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Braswell M/D part support.
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if SOC_INTEL_BRASWELL
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_RAMSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_VERSTAGE_X86_32
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select BOOT_DEVICE_SUPPORTS_WRITES
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select CACHE_MRC_SETTINGS
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
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select COLLECT_TIMESTAMPS
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select SUPPORT_CPU_UCODE_IN_CBFS
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select MICROCODE_BLOB_NOT_IN_BLOB_REPO
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select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
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select HAVE_MONOTONIC_TIMER
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select HAVE_SMI_HANDLER
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select NO_FIXED_XIP_ROM_SIZE
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select PARALLEL_MP
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select PCIEXP_ASPM
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select PCIEXP_CLK_PM
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select PCIEXP_COMMON_CLOCK
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select PLATFORM_USES_FSP1_1
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select REG_SCRIPT
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select RTC
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
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select SOC_INTEL_COMMON_BLOCK
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select SOC_INTEL_COMMON_BLOCK_HDA
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select SOC_INTEL_COMMON_RESET
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select SMM_TSEG
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select SMP
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select SPI_FLASH
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select SSE2
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select TSC_CONSTANT_RATE
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select TSC_MONOTONIC_TIMER
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select TSC_SYNC_MFENCE
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select UDELAY_TSC
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select USE_GENERIC_FSP_CAR_INC
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select INTEL_DESCRIPTOR_MODE_CAPABLE
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select HAVE_SPI_CONSOLE_SUPPORT
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select HAVE_FSP_GOP
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select GENERIC_GPIO_LIB
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select INTEL_GMA_ACPI
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select INTEL_GMA_SWSMISCI
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select CPU_INTEL_COMMON
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select SOUTHBRIDGE_INTEL_COMMON_SMBUS
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config VBOOT
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select VBOOT_MUST_REQUEST_DISPLAY
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select VBOOT_STARTS_IN_ROMSTAGE
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config BOOTBLOCK_CPU_INIT
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string
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default "soc/intel/braswell/bootblock/bootblock.c"
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config MMCONF_BASE_ADDRESS
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hex
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default 0xe0000000
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config MAX_CPUS
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int
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default 4
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config CPU_ADDR_BITS
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int
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default 36
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config SMM_TSEG_SIZE
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hex
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default 0x800000
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config SMM_RESERVED_SIZE
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hex
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default 0x100000
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# Cache As RAM region layout:
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#
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# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE
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# | Stack |
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# | | |
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# | v |
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# +-------------+
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# | ^ |
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# | | |
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# | CAR Globals |
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# +-------------+ DCACHE_RAM_BASE
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#
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config DCACHE_RAM_BASE
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hex
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default 0xfef00000
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config DCACHE_RAM_SIZE
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hex
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default 0x4000
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help
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The size of the cache-as-ram region required during bootblock
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and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
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must add up to a power of 2.
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config RESET_ON_INVALID_RAMSTAGE_CACHE
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bool "Reset the system on S3 wake when ramstage cache invalid."
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default n
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help
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The haswell romstage code caches the loaded ramstage program
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in SMM space. On S3 wake the romstage will copy over a fresh
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ramstage that was cached in the SMM space. This option determines
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the action to take when the ramstage cache is invalid. If selected
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the system will reset otherwise the ramstage will be reloaded from
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cbfs.
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config ENABLE_BUILTIN_COM1
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bool "Enable builtin COM1 Serial Port"
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default n
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help
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The PMC has a legacy COM1 serial port. Choose this option to
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configure the pads and enable it. This serial port can be used for
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the debug console.
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config IED_REGION_SIZE
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hex
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default 0x400000
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config DISABLE_HPET
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bool "Disable the HPET device"
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default n
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help
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Enable this to disable the HPET support
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Solves the Linux MP-BIOS bug timer not connected.
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config USE_GOOGLE_FSP
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bool
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help
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Select this to use Google's custom Braswell FSP header/binary
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instead of the public release on Github. Only google/cyan
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variants require this; all other boards should use the public release.
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config FSP_HEADER_PATH
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string
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default "$(src)/vendorcode/intel/fsp/fsp1_1/braswell" if USE_GOOGLE_FSP
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default "3rdparty/fsp/BraswellFspBinPkg/Include/"
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help
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Location of FSP header file FspUpdVpd.h
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endif
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