3ff14a0c85
Change-Id: I3e76726bb77f0277ab5776ae9d3d42b7eb389fe3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/19603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
112 lines
3.5 KiB
C
112 lines
3.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <assert.h>
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#include <intelblocks/gpio.h>
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#include <intelblocks/pcr.h>
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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static const struct reset_mapping rst_map[] = {
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{ .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
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{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
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{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
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};
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static const struct pad_community glk_gpio_communities[] = {
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{
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.port = PID_GPIO_NW,
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.first_pad = NW_OFFSET,
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.last_pad = GPIO_214,
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.num_gpi_regs = NUM_NW_GPI_REGS,
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.gpi_status_offset = 0,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
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.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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.name = "GPIO_NORTHWEST",
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.acpi_path = "\\_SB.GPO0",
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.reset_map = rst_map,
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.num_reset_vals = ARRAY_SIZE(rst_map),
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}, {
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.port = PID_GPIO_N,
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.first_pad = N_OFFSET,
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.last_pad = GPIO_155,
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.num_gpi_regs = NUM_N_GPI_REGS,
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.gpi_status_offset = NUM_NW_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
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.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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.name = "GPIO_NORTH",
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.acpi_path = "\\_SB.GPO1",
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.reset_map = rst_map,
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.num_reset_vals = ARRAY_SIZE(rst_map),
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}, {
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.port = PID_GPIO_AUDIO,
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.first_pad = AUDIO_OFFSET,
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.last_pad = GPIO_175,
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.num_gpi_regs = NUM_AUDIO_GPI_REGS,
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.gpi_status_offset = NUM_NW_GPI_REGS + NUM_N_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
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.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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.name = "GPIO_AUDIO",
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.acpi_path = "\\_SB.GPO2",
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.reset_map = rst_map,
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.num_reset_vals = ARRAY_SIZE(rst_map),
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}, {
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.port = PID_GPIO_SCC,
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.first_pad = SCC_OFFSET,
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.last_pad = GPIO_209,
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.num_gpi_regs = NUM_SCC_GPI_REGS,
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.gpi_status_offset = NUM_NW_GPI_REGS + NUM_N_GPI_REGS +
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NUM_AUDIO_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
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.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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.name = "GPIO_SCC",
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.acpi_path = "\\_SB.GPO3",
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.reset_map = rst_map,
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.num_reset_vals = ARRAY_SIZE(rst_map),
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},
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};
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const struct pad_community *soc_gpio_get_community(size_t *num_communities)
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{
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*num_communities = ARRAY_SIZE(glk_gpio_communities);
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return glk_gpio_communities;
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}
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const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
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{
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static const struct pmc_to_gpio_route routes[] = {
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{ PMC_GPE_NW_31_0, GPIO_GPE_NW_31_0 },
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{ PMC_GPE_NW_63_32, GPIO_GPE_NW_63_32 },
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{ PMC_GPE_N_31_0, GPIO_GPE_N_31_0 },
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{ PMC_GPE_N_63_32, GPIO_GPE_N_63_32 },
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{ PMC_GPE_N_95_64, GPIO_GPE_N_95_64 },
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};
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*num = ARRAY_SIZE(routes);
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return routes;
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}
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