4e9bb3308e
Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space. Some platforms have a different way of mapping the PCI config
space to memory. This patch renames the following configs to
make it clear that these configs are ECAM-specific:
- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH
Please refer to CB:57861 "Proposed coreboot Changes" for more
details.
BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
Make sure Jenkins verifies that builds on other boards
Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
95 lines
2.3 KiB
C
95 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <stdint.h>
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#include <console/console.h>
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <device/pci_type.h>
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u8 *const pci_mmconf = (void *)(uintptr_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS;
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/**
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* Given a device, a capability type, and a last position, return the next
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* matching capability. Always start at the head of the list.
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*
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* @param dev Pointer to the device structure.
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* @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for.
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* @param last Location of the PCI capability register to start from.
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* @return The next matching capability.
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*/
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u16 pci_s_find_next_capability(pci_devfn_t dev, u16 cap, u16 last)
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{
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u16 pos = 0;
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u16 status;
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int reps = 48;
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status = pci_s_read_config16(dev, PCI_STATUS);
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if (!(status & PCI_STATUS_CAP_LIST))
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return 0;
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u8 hdr_type = pci_s_read_config8(dev, PCI_HEADER_TYPE);
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switch (hdr_type & 0x7f) {
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case PCI_HEADER_TYPE_NORMAL:
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case PCI_HEADER_TYPE_BRIDGE:
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pos = PCI_CAPABILITY_LIST;
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break;
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case PCI_HEADER_TYPE_CARDBUS:
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pos = PCI_CB_CAPABILITY_LIST;
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break;
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default:
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return 0;
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}
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pos = pci_s_read_config8(dev, pos);
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while (reps-- && (pos >= 0x40)) { /* Loop through the linked list. */
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int this_cap;
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pos &= ~3;
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this_cap = pci_s_read_config8(dev, pos + PCI_CAP_LIST_ID);
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if (this_cap == 0xff)
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break;
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if (!last && (this_cap == cap))
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return pos;
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if (last == pos)
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last = 0;
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pos = pci_s_read_config8(dev, pos + PCI_CAP_LIST_NEXT);
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}
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return 0;
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}
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/**
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* Given a device, and a capability type, return the next matching
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* capability. Always start at the head of the list.
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*
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* @param dev Pointer to the device structure.
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* @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for.
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* @return The next matching capability.
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*/
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u16 pci_s_find_capability(pci_devfn_t dev, u16 cap)
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{
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return pci_s_find_next_capability(dev, cap, 0);
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}
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void __noreturn pcidev_die(void)
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{
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die("PCI: dev is NULL!\n");
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}
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bool pci_dev_is_wake_source(pci_devfn_t dev)
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{
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unsigned int pm_cap;
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uint16_t pmcs;
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pm_cap = pci_s_find_capability(dev, PCI_CAP_ID_PM);
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if (!pm_cap)
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return false;
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pmcs = pci_s_read_config16(dev, pm_cap + PCI_PM_CTRL);
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/* PCI Device is a wake source if PME_ENABLE and PME_STATUS are set in PMCS register. */
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return (pmcs & PCI_PM_CTRL_PME_ENABLE) && (pmcs & PCI_PM_CTRL_PME_STATUS);
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}
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