c3c55210ee
Except for whitespace and varying casts the codes were the same when implemented. Platforms that did not implement this are tagged with ACPI_NO_SMI_GNVS. Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
88 lines
2.1 KiB
C
88 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/device.h>
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#include <device/pci.h>
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#include <console/console.h>
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#include <arch/io.h>
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#include <cpu/x86/smm.h>
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#include <cpu/intel/smm_reloc.h>
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#include <soc/iomap.h>
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#include <soc/pch.h>
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#include <soc/pm.h>
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void smm_southbridge_clear_state(void)
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{
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u32 smi_en;
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printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
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printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", ACPI_BASE_ADDRESS);
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smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN);
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if (smi_en & APMC_EN) {
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printk(BIOS_INFO, "SMI# handler already enabled?\n");
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return;
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}
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printk(BIOS_DEBUG, "\n");
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/* Dump and clear status registers */
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clear_smi_status();
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clear_pm1_status();
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clear_tco_status();
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clear_gpe_status();
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}
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static void smm_southbridge_enable(uint16_t pm1_events)
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{
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printk(BIOS_DEBUG, "Enabling SMIs.\n");
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/* Configure events */
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enable_pm1(pm1_events);
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disable_gpe(PME_B0_EN);
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/* Enable SMI generation:
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* - on APMC writes (io 0xb2)
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* - on writes to SLP_EN (sleep states)
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* - on writes to GBL_RLS (bios commands)
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* No SMIs:
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* - on microcontroller writes (io 0x62/0x66)
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* - on TCO events
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*/
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enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
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}
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void global_smi_enable(void)
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{
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smm_southbridge_enable(PWRBTN_EN | GBL_EN);
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}
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static void __unused southbridge_trigger_smi(void)
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{
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/**
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* There are several methods of raising a controlled SMI# via
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* software, among them:
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* - Writes to io 0xb2 (APMC)
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* - Writes to the Local Apic ICR with Delivery mode SMI.
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*
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* Using the local APIC is a bit more tricky. According to
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* AMD Family 11 Processor BKDG no destination shorthand must be
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* used.
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* The whole SMM initialization is quite a bit hardware specific, so
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* I'm not too worried about the better of the methods at the moment
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*/
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/* raise an SMI interrupt */
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printk(BIOS_SPEW, " ... raise SMI#\n");
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apm_control(APM_CNT_NOOP_SMI);
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}
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static void __unused southbridge_clear_smi_status(void)
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{
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/* Clear SMI status */
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clear_smi_status();
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/* Clear PM1 status */
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clear_pm1_status();
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/* Set EOS bit so other SMIs can occur. */
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enable_smi(EOS);
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}
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