Duncan Laurie 138f2cede4 haswell: remove GPIO60 memory reset gate on S3 transition ... This is no longer tied to a GPIO but has a proper chipset pin. Change-Id: Iba70338e8c67e3c3c1cb32e69bfea1282fda8cb5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2643 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>		2013-03-14 06:36:21 +01:00
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arch	Eliminate do_div().	2013-03-08 23:14:26 +01:00
console	Eliminate do_div().	2013-03-08 23:14:26 +01:00
cpu	haswell: Properly Guard Engergy Policy by CPUID	2013-03-14 05:10:32 +01:00
device	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	2013-03-01 10:16:08 +01:00
drivers	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	2013-03-01 10:16:08 +01:00
ec	Support ITE IT8518 embedded controller running Quanta's firmware	2013-03-14 04:54:21 +01:00
include	haswell: add PCI id support	2013-03-14 05:10:13 +01:00
lib	Eliminate do_div().	2013-03-08 23:14:26 +01:00
mainboard	basking ridge: update gpio, spd addresses, and OC	2013-03-14 05:09:29 +01:00
northbridge	haswell: remove explicit pcie config accesses	2013-03-14 06:35:48 +01:00
southbridge	haswell: remove GPIO60 memory reset gate on S3 transition	2013-03-14 06:36:21 +01:00
superio	AMD SB800: don't switch clock from 14 to 48 MHz for smscsuperio	2013-03-06 19:07:28 +01:00
vendorcode	AGESA: Fix CR0_PE bit define	2013-03-08 07:30:06 +01:00
Kconfig	bump SeaBIOS to 1.7.2.1	2013-03-04 11:00:17 +01:00