Kyösti Mälkki 140087f84f CPU: Declare cpu_phys_address_size() for all arch ... Resource allocator and 64-bit PCI BARs will need it and PCI use is not really restricted to x86. Change-Id: Ie97f0f73380118f43ec6271aed5617d62a4f5532 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17733 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2016-12-06 20:53:45 +01:00
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acpi	src/acpi: Capitalize ACPI and SATA	2016-07-31 19:25:40 +02:00
arch	CPU: Declare cpu_phys_address_size() for all arch	2016-12-06 20:53:45 +01:00
commonlib	soc/intel/common: Add suppport for Extended VBT	2016-12-02 21:51:01 +01:00
console	Hook up libhwbase in ramstage	2016-11-29 23:45:40 +01:00
cpu	CPU: Declare cpu_phys_address_size() for all arch	2016-12-06 20:53:45 +01:00
device	PCI ops: Remove pci_mmio_xx() in ramstage	2016-12-06 20:47:49 +01:00
drivers	spi_flash: Make a deep copy of spi_slave structure	2016-12-06 07:17:28 +01:00
ec	spi: Pass pointer to spi_slave structure in spi_setup_slave	2016-12-05 03:28:06 +01:00
include	CPU: Declare cpu_phys_address_size() for all arch	2016-12-06 20:53:45 +01:00
lib	lib/nhlt: add support for setting the oem_revision	2016-12-01 08:17:42 +01:00
mainboard	CPU: Move SMM prototypes under x86	2016-12-06 20:53:30 +01:00
northbridge	CPU: Declare cpu_phys_address_size() for all arch	2016-12-06 20:53:45 +01:00
soc	CPU: Declare cpu_phys_address_size() for all arch	2016-12-06 20:53:45 +01:00
southbridge	PCI ops: Define read-modify-write routines globally	2016-12-06 20:45:22 +01:00
superio	sio/nuvoton: Include generic nuvoton driver in bootblock stage	2016-11-28 20:33:21 +01:00
vboot	commonlib/include: remove NEED_VB20_INTERNALS	2016-11-19 16:57:27 +01:00
vendorcode	vendorcode/siemens: Ensure a given info block is available for a field	2016-12-06 09:59:11 +01:00
Kconfig	mb/intel/kblrvp: Add Variant board support for KBLRVP	2016-11-30 17:03:44 +01:00