4bab6e79b0
Change-Id: I6ea9b9d2353c0d767c837e6d629b45f23b306f6e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14599 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
87 lines
2.4 KiB
C
87 lines
2.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2009-2010 iWave Systems
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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/* PCI Configuration Space (D31:F1): IDE */
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#define INTR_LN 0x3c
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#define IDE_TIM_PRI 0x80 /* IDE timings, primary */
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extern int sch_port_access_read(int port, int reg, int bytes);
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static void ide_init(struct device *dev)
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{
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u32 ideTimingConfig, reg32;
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printk(BIOS_DEBUG, "sch_ide: initializing... ");
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reg32 = pci_read_config32(dev, PCI_COMMAND);
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pci_write_config32(dev, PCI_COMMAND,
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reg32 | PCI_COMMAND_IO | PCI_COMMAND_MASTER);
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/* Program the clock. */
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if (sch_port_access_read(5, 3, 4) & (1 << 3)) {
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/* 533MHz, Read PCI MC register */
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reg32 = pci_read_config32(dev, 0x60);
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pci_write_config32(dev, 0x60, reg32 | 1);
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} else {
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/* 400MHz */
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reg32 = pci_read_config32(dev, 0x60);
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reg32 &= ~1;
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pci_write_config32(dev, 0x60, reg32);
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}
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/* Enable primary IDE interface. 80=04 81=00 82=02 83=80 */
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ideTimingConfig = 0x80020000;
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printk(BIOS_DEBUG, "IDE0 ");
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pci_write_config32(dev, IDE_TIM_PRI, ideTimingConfig);
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/* Set Interrupt Line. */
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/* Interrupt Pin is set by D31IP.PIP */
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printk(BIOS_DEBUG, "\n");
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}
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static void ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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{
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if (!vendor || !device) {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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pci_read_config32(dev, PCI_VENDOR_ID));
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} else {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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}
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static struct pci_operations ide_pci_ops = {
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.set_subsystem = ide_set_subsystem,
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};
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static struct device_operations ide_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = ide_init,
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.scan_bus = 0,
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.ops_pci = &ide_pci_ops,
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};
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static const struct pci_driver sch_ide __pci_driver = {
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.ops = &ide_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = 0x811A,
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};
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