coreboot-kgpe-d16/src/mainboard/supermicro/h8dmr_fam10/README
Patrick Georgi 784544b934 Remove XIP_ROM_BASE
The base is now calculated automatically, and all mentions of that
config option were typical anyway (4GB - XIP_ROM_SIZE).

Change-Id: Icdf908dc043719f3810f7b5b85ad9938f362ea40
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/366
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-01 19:06:23 +01:00

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There are a number of outstanding issues:
* I'm seeing toolchain issues. I can't get this tree to compile correctly with
gcc 4.3 (32 bit) - there is an optimization issue where certain parts of the
CBFS code execute very slowly. With gcc 3.4 (32 bit) that slowness
disappears. This is probably not a problem related to this port specifically.
* setting CONFIG_DEFAULT_CONSOLE_LOGLEVEL lower than 8 simply hangs the boot
shortly after the warm reset triggered by the MCP55 code. I think this too
might be a toolchain problem (but I see it on gcc 3.4 as well as 4.3).
* during startup, the CPU cores talk through each other on serial for a
while. Again, not an issue specific to this port.
* to avoid very slow LZMA decompression I use this port with LZMA compression
disabled in CBFS. I'm not sure what's causing this particular slowness.
See also this thread: http://www.coreboot.org/pipermail/coreboot/2009-September/052107.html
Ward, 2009-09-22