Furquan Shaikh 2d602098f9 mb/google/octopus: Configure H1 interrupt pad using Rx level config ... This change configures GPIO_63 (which is used for H1 interrupts) as Rx Level. This ensures that the signal gets passed on to the next logic state as is and the APIC entry can be configured to trigger interrupt on level or edge as per the kernel driver expectation. TEST=Verified that no H1 interrupt timeouts are seen with 100 iterations of warm and 100 iterations of cold reboot. Change-Id: I7aac30300a4251d9b40276dcca7ebc6a6d814c40 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2018-09-06 22:45:23 +00:00
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variants	mb/google/octopus: Configure H1 interrupt pad using Rx level config	2018-09-06 22:45:23 +00:00
acpi_tables.c
board_info.txt
bootblock.c	mb/google/octopus: Perform EC init before bootblock gpio configuration	2018-07-29 03:51:00 +00:00
chromeos.c	mb/google/octopus: Configure EC_IN_RW correctly	2018-06-20 18:28:46 +00:00
chromeos.fmd	mb/google/octopus: Use unused space in RO_SECTION for COREBOOT region	2018-07-23 03:41:34 +00:00
dsdt.asl	mb/google/octopus: Add dptf.asl in dsdt.asl	2018-04-26 21:32:10 +00:00
ec.c
Kconfig	mb/google/octopus: Enable SAR config for Intel 9560 module	2018-08-13 12:16:15 +00:00
Kconfig.name	mb/google/octopus: Enable EC SW sync for all	2018-08-02 10:51:42 +00:00
mainboard.c	mb/google/octopus: Add null pointer check	2018-08-23 14:36:20 +00:00
Makefile.inc
romstage.c	mb/google/octopus: add support for fetching DRAM part number from CBI	2018-08-09 16:56:57 +00:00
smihandler.c	mb/google/octopus: Enable logging of EC wake sources in S0ix	2018-06-26 20:40:27 +00:00