d2d9021543
This patch brings the feature of disabling RAPL to common code. It replaces the current solution for APL and EHL. For special case if RAPL disabling is only working via changes in MCHBAR a new config switch was introduced. Test: Boot mc_apl4/5 with this patch and ensure that the relevant bits in MSR 0x610 are the same as before the patch. Change-Id: I2098ddcd2f19e3ebd87ef00c544e1427674f5e84 Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
64 lines
1.7 KiB
C
64 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <delay.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <intelblocks/power_limit.h>
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#include <intelblocks/systemagent.h>
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#include <soc/iomap.h>
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#include <soc/soc_chip.h>
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#include <soc/systemagent.h>
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/*
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* SoC implementation
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*
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* Add all known fixed memory ranges for Host Controller/Memory
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* controller.
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*/
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void soc_add_fixed_mmio_resources(struct device *dev, int *index)
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{
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static const struct sa_mmio_descriptor soc_fixed_resources[] = {
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{ PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
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"PCIEXBAR" },
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{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
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{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
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{ EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
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{ REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
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{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
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};
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sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
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ARRAY_SIZE(soc_fixed_resources));
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/* Add Vt-d resources if VT-d is enabled */
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if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
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return;
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sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
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ARRAY_SIZE(soc_vtd_resources));
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}
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/*
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* SoC implementation
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*
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* Perform System Agent Initialization during Ramstage phase.
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*/
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void soc_systemagent_init(struct device *dev)
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{
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struct soc_power_limits_config *soc_config;
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config_t *config;
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/* Enable Power Aware Interrupt Routing */
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enable_power_aware_intr();
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/* Enable BIOS Reset CPL */
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enable_bios_reset_cpl();
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mdelay(1);
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config = config_of_soc();
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soc_config = &config->power_limits_config;
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set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
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}
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