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coreboot-kgpe-d16/Documentation/arch/x86/index.md
Patrick Rudolph 03a79520d6 cpu/x86/smm: Add support for long mode 
Enable long mode in SMM handler.
x86_32 isn't affected by this change.

As the rsm instruction used to leave SMM doesn't restore MSR registers,
drop back to protected mode after running the smi_handler and restore
IA32_EFER MSR (which enables long mode support) to previous value.

NOTE: This commit does NOT introduce a new security model. It uses the
      same page tables as the remaining firmware does.
      This can be a security risk if someone is able to manipulate the
      page tables stored in ROM at runtime. USE FOR TESTING ONLY!

Tested on Qemu Q35.

Change-Id: I8bba4af4688c723fc079ae905dac95f57ea956f8
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35681
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 07:28:32 +00:00

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x86 architecture documentation

This section contains documentation about coreboot on x86 architecture.

State of x86_64 support

At the moment there's no single board that supports x86_64 or to be exact ARCH_RAMSTAGE_X86_64 and ARCH_ROMSTAGE_X86_64.

In order to add support for x86_64 the following assumptions are made:

  • The CPU supports long mode
  • All memory returned by malloc must be below 4GiB in physical memory
  • All code that is to be run must be below 4GiB in physical memory
  • The high dword of pointers is always zero
  • The reference implementation is qemu
  • The CPU supports 1GiB hugepages

Assuptions for all stages using the reference implementation

  • 0-4GiB are identity mapped using 2MiB-pages as WB
  • Memory above 4GiB isn't accessible
  • page tables reside in memory mapped ROM
  • A stage can install new page tables in RAM

Page tables

Page tables are generated by a tool in util/pgtblgen/pgtblgen. It writes the page tables to a file which is then included into the CBFS as file called pagetables.

To generate the static page tables it must know the physical address where to place the file.

The page tables contains the following structure:

  • PML4E pointing to PDPE
  • PDPE with $n entries each pointing to PDE
  • $n PDEs with 512 entries each

At the moment $n is 4, which results in identity mapping the lower 4 GiB.

Steps to add basic support for x86_64

  • Add x86_64 toolchain support - DONE
  • Fix compilation errors - DONE
  • Fix linker errors - TODO
  • Add x86_64 rmodule support - DONE
  • Add x86_64 exception handlers - DONE
  • Setup page tables for long mode - DONE
  • Add assembly code for long mode - DONE
  • Add assembly code for SMM - DONE
  • Add assembly code for postcar stage - TODO
  • Add assembly code to return to protected mode - TODO
  • Implement reference code for mainboard emulation/qemu-q35 - TODO

Future work

  1. Fine grained page tables for SMM:
    • Must not have execute and write permissions for the same page.
    • Must allow only that TSEG pages can be marked executable
    • Must reside in SMRAM
  2. Support 64bit PCI BARs above 4GiB
  3. Place and run code above 4GiB

Porting other boards

  • Fix compilation errors
  • Test how well CAR works with x86_64 and paging
  • Improve mode switches
  • Test libgfxinit / VGA Option ROMs / FSP