1222a73205
Add Initial pieces of code to support fsp2.0 in skylake keeping the fsp1.1 flow intact. The soc/romstage.h and soc/ramstage.h have a reference to fsp driver includes, so split these header files for each version of FSP driver. Add the below files, car_stage.S: Add romstage entry point (car_stage_entry). This calls into romstage_fsp20.c and aslo handles the car teardown. romstage_fsp20.c: Call fsp_memory_init() and also has the callback for filling memory init parameters. Also add monotonic_timer.c to verstage. With this patchset and relevant change in kunimitsu mainboard, we are able to boot to romstage. TEST= Build and Boot Kunimitsu with PLATFORM_USES_FSP1_1 Build and Boot Kunimitsu to romstage with PLATFORM_USES_FSP2_0 Change-Id: I4309c8d4369c84d2bd1b13e8ab7bfeaaec645520 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16267 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
110 lines
3 KiB
C
110 lines
3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <fsp/api.h>
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#include <soc/ramstage.h>
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#include <soc/vr_config.h>
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/* Default values for domain configuration. PSI3 and PSI4 are disabled. */
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static const struct vr_config default_configs[NUM_VR_DOMAINS] = {
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[VR_SYSTEM_AGENT] = {
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(4),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 0,
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.psi4enable = 0,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(7),
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.voltage_limit = 1520,
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},
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[VR_IA_CORE] = {
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 0,
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.psi4enable = 0,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(34),
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.voltage_limit = 1520,
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},
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[VR_RING] = {
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 0,
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.psi4enable = 0,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(34),
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.voltage_limit = 1520,
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},
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[VR_GT_UNSLICED] = {
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 0,
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.psi4enable = 0,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(35),
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.voltage_limit = 1520,
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},
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[VR_GT_SLICED] = {
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 0,
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.psi4enable = 0,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(35),
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.voltage_limit = 1520,
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},
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};
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void fill_vr_domain_config(void *params,
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int domain, const struct vr_config *chip_cfg)
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{
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FSP_SIL_UPD *vr_params = (FSP_SIL_UPD *)params;
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const struct vr_config *cfg;
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if (domain < 0 || domain >= NUM_VR_DOMAINS)
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return;
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/* Use device tree override if requested. */
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if (chip_cfg->vr_config_enable)
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cfg = chip_cfg;
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else
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cfg = &default_configs[domain];
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vr_params->VrConfigEnable[domain] = cfg->vr_config_enable;
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vr_params->Psi1Threshold[domain] = cfg->psi1threshold;
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vr_params->Psi2Threshold[domain] = cfg->psi2threshold;
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vr_params->Psi3Threshold[domain] = cfg->psi3threshold;
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vr_params->Psi3Enable[domain] = cfg->psi3enable;
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vr_params->Psi4Enable[domain] = cfg->psi4enable;
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vr_params->ImonSlope[domain] = cfg->imon_slope;
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vr_params->ImonOffset[domain] = cfg->imon_offset;
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vr_params->IccMax[domain] = cfg->icc_max;
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vr_params->VrVoltageLimit[domain] = cfg->voltage_limit;
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}
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