Wisley Chen 1852303682 util: Add DDR4 generic SPD for MT40A512M16TB-062E:R ... Add SPD support for DDR4 memory part BUG=b:190020997 TEST=none Change-Id: I423131cb674e1e5ec699c7a28e5b5e6746247b2a Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55164 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-06-14 05:27:39 +00:00
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acpi	acpi: drop weak implementation of acpi_soc_get_bert_region	2021-06-08 18:25:20 +00:00
arch	arch/x86/mptable: Add smp_write_ioapic_from_hw()	2021-06-12 15:49:35 +00:00
commonlib	commonlib/lz4_wrapper.c: do not use bitfields	2021-06-11 07:41:41 +00:00
console	tests/console: Add tests for log message routing behavior	2021-06-10 19:27:44 +00:00
cpu	cpu/x86/lapic: Replace LOCAL_APIC_ADDR references	2021-06-11 07:11:43 +00:00
device	device/pnp: Always provide `pnp_unset_and_set_config`	2021-06-10 05:38:13 +00:00
drivers	drivers/intel/gma: Restructure IGD opregion init code	2021-06-11 07:38:13 +00:00
ec	ec/google/chromeec: Separate SMBIOS SKU functions	2021-06-09 05:18:35 +00:00
include	lib/hardwaremain.c: Hide preprocessor guards in header	2021-06-14 05:20:05 +00:00
lib	lib/hardwaremain: Print individual boot state callback durations	2021-06-14 05:20:59 +00:00
mainboard	mb/google/volteer/var/trondo: Update gpio settings	2021-06-14 05:27:04 +00:00
northbridge	nb/haswell/gma: Add Desktop GT1.5 (HD 4400) Device ID	2021-06-10 05:37:51 +00:00
security	security/vboot: Add timestamps when loading verstage	2021-06-14 05:11:07 +00:00
soc	util: Add DDR4 generic SPD for MT40A512M16TB-062E:R	2021-06-14 05:27:39 +00:00
southbridge	arch/x86/ioapic: Add get_ioapic_id() and get_ioapic_version()	2021-06-12 15:48:49 +00:00
superio	src: Retype option API to use unsigned integers	2021-05-06 14:48:15 +00:00
vendorcode	soc/amd/cezanne: Supply SMBIOS/DMI Type 17 data	2021-06-13 09:55:39 +00:00
Kconfig	option: Allow mainboards to implement the API	2021-05-28 11:37:25 +00:00