Kerry Sheh 19329c90d3 Inagua: mainboard specific GPIO setting ... Pcie device connected to Hudson/sb800 southbridge GPP training can works, by applying this mainbaind specific GPIO PCIE De-Assert setting. Change-Id: I563b2e6354a958a28f5d0162e7a4d60aa437fb9b Signed-off-by: Kerry Sheh <shekairui@gmail.com> Signed-off-by: Kerry Sheh <kerry.she@amd.com> Reviewed-on: http://review.coreboot.org/543 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>		2012-02-07 00:24:48 +01:00
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arch/x86	Move SeaBIOS output out of coreboot source tree	2012-02-07 00:21:03 +01:00
boot	selfboot: Don't include unneeded ip_checksum.h	2011-11-08 21:21:55 +01:00
console	trivial:change the value type of POST_PORT in Kconfig from int to hex	2011-12-26 08:52:07 +01:00
cpu	post code: Replaced hard-coded post code with macro	2012-01-23 22:50:56 +01:00
devices	Add OPROM mapping support to coreboot	2012-02-07 00:09:58 +01:00
drivers	adm1026: removed prototype	2012-01-21 18:48:03 +01:00
ec	X60/T60: Add option to enable/disable bluetooth	2012-01-31 18:03:40 +01:00
include	Add OPROM mapping support to coreboot	2012-02-07 00:09:58 +01:00
lib	lib: add ram_check_nodie	2012-01-12 13:26:29 +01:00
mainboard	Inagua: mainboard specific GPIO setting	2012-02-07 00:24:48 +01:00
northbridge	Add Intel i5000 Memory Controller Hub	2012-02-02 13:49:33 +01:00
pc80	vga: removed inclusion of .c files	2012-01-27 20:07:00 +01:00
southbridge	i3100: configure pci irqs	2012-02-02 16:01:47 +01:00
superio	SIO: condition compile Nuvoton WPCM450 early_init.c	2012-02-05 17:45:08 +01:00
vendorcode	SB700 southbridge: AMD SB700/SP5100 southbridge CIMX code	2012-02-02 15:05:36 +01:00
Kconfig	Move SeaBIOS output out of coreboot source tree	2012-02-07 00:21:03 +01:00
Kconfig.deprecated_options	Unify ID_SECTION_OFFSET and mark it deprecated	2012-01-18 11:21:39 +01:00