ce9e21a0ea
Add a bootblock which builds with C_ENVIRONMENT_BOOTBLOCK selected. This is the first piece in supporting FSP 2.0. Move esraminit from romstage into the bootblock. Replace cache_as_ram with car_stage_entry.S and code in romstage.c TEST=Build and run on Galileo Gen2 Change-Id: I14d2af2adb6e75d4bff1ebfb863196df04d07daf Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15132 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
279 lines
7.2 KiB
Text
279 lines
7.2 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2015-2016 Intel Corp.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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config SOC_INTEL_QUARK
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bool
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help
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Intel Quark support
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if SOC_INTEL_QUARK
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_RAMSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_VERSTAGE_X86_32
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select BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP
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select C_ENVIRONMENT_BOOTBLOCK
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select REG_SCRIPT
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select SOC_INTEL_COMMON
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select SOC_SETS_MTRRS
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select TSC_CONSTANT_RATE
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select UART_OVERRIDE_REFCLK
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select UDELAY_TSC
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select UNCOMPRESSED_RAMSTAGE
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select USE_MARCH_586
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#####
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# Debug serial output
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# The following options configure the debug serial port
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#####
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config ENABLE_BUILTIN_HSUART0
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bool "Enable built-in HSUART0"
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default n
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select NO_UART_ON_SUPERIO
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select DRIVERS_UART_8250MEM_32
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help
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The Quark SoC has two HSUART. Choose this option to configure the pads
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and enable HSUART0, which can be used for the debug console.
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config ENABLE_BUILTIN_HSUART1
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bool "Enable built-in HSUART1"
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default n
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depends on ! ENABLE_BUILTIN_HSUART0
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select NO_UART_ON_SUPERIO
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select DRIVERS_UART_8250MEM_32
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help
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The Quark SoC has two HSUART. Choose this option to configure the pads
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and enable HSUART1, which can be used for the debug console.
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config TTYS0_BASE
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hex "HSUART Base Address"
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default 0xA0019000
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depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1
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help
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Memory mapped MMIO of HSUART.
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config TTYS0_LCS
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int
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default 3
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depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1
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# Console: PCI UART bus 0 << 20, device 20 << 15, function x << 12
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# Valid bit, PCI UART in use: 1 << 31
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config UART_PCI_ADDR
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hex
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default 0x800a1000 if ENABLE_BUILTIN_HSUART0
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default 0x800a5000 if ENABLE_BUILTIN_HSUART1
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depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1
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#####
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# Debug support
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# The following options provide debug support for the Quark coreboot
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# code. The SD LED is used as a binary marker to determine if a
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# specific point in the execution flow has been reached.
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#####
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config ENABLE_DEBUG_LED
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bool
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default n
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help
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Enable the use of the SD LED for early debugging before serial output
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is available. Setting this LED indicates that control has reached the
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desired check point.
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config ENABLE_DEBUG_LED_ESRAM
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bool "SD LED indicates ESRAM initialized"
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default n
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select ENABLE_DEBUG_LED
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help
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Indicate that ESRAM has been successfully initialized.
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config ENABLE_DEBUG_LED_FINDFSP
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bool "SD LED indicates fsp.bin file was found"
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default n
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select ENABLE_DEBUG_LED
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help
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Indicate that fsp.bin was found.
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config ENABLE_DEBUG_LED_TEMPRAMINIT
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bool "SD LED indicates TempRamInit was successful"
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default n
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select ENABLE_DEBUG_LED
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help
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Indicate that TempRamInit was successful.
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#####
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# ESRAM layout
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# Specify the portion of the ESRAM for coreboot to use as its data area.
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#####
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config DCACHE_RAM_BASE
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hex
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default 0x80070000
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config DCACHE_RAM_SIZE
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hex
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default 0x00008000
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#####
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# Flash layout
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# Specify the size of the coreboot file system in the read-only
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# (recovery) portion of the flash part.
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#####
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config CBFS_SIZE
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hex
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default 0x200000
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help
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Specify the size of the coreboot file system in the read-only (recovery)
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portion of the flash part. On Quark systems the firmware image stores
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more than just coreboot, including:
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- The chipset microcode (RMU) binary file located at 0xFFF00000
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- Intel Trusted Execution Engine firmware
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#####
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# FSP binary
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# The following options control the FSP binary file placement in
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# the flash image and ESRAM. This file is required by the Quark
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# SoC code to boot coreboot and its payload.
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#####
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config ADD_FSP_RAW_BIN
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bool "Add the Intel FSP binary to the flash image without relocation"
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default n
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depends on PLATFORM_USES_FSP1_1
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help
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Select this option to add an Intel FSP binary to
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the resulting coreboot image.
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Note: Without this binary, coreboot builds relying on the FSP
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will not boot
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config FSP_FILE
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string "Intel FSP binary path and filename"
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default "3rdparty/blobs/soc/intel/quark/fsp.bin"
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depends on PLATFORM_USES_FSP1_1
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depends on ADD_FSP_RAW_BIN
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help
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The path and filename of the Intel FSP binary for this platform.
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config FSP_IMAGE_ID_STRING
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string "8 byte platform string identifying the FSP platform"
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default "QUK-FSP0"
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depends on PLATFORM_USES_FSP1_1
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help
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8 ASCII character byte signature string that will help match the FSP
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binary to a supported hardware configuration.
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config FSP_LOC
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hex
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default 0xfff80000
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depends on PLATFORM_USES_FSP1_1
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help
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The location in CBFS that the FSP is located. This must match the
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value that is set in the FSP binary. If the FSP needs to be moved,
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rebase the FSP with Intel's BCT (tool).
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config FSP_ESRAM_LOC
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hex
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default 0x80000000
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depends on PLATFORM_USES_FSP1_1
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help
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The location in ESRAM where a copy of the FSP binary is placed.
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config RELOCATE_FSP_INTO_DRAM
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bool "Relocate FSP into DRAM"
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default n
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depends on PLATFORM_USES_FSP1_1
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help
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Relocate the FSP binary into DRAM before the call to SiliconInit.
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#####
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# FSP PDAT binary
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# The following options control the FSP platform data binary
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# file placement in the flash image.
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#####
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config ADD_FSP_PDAT_FILE
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bool "Should the PDAT binary be added to the flash image?"
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default n
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depends on PLATFORM_USES_FSP1_1
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help
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The PDAT file is required for the FSP 1.1 binary
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config FSP_PDAT_FILE
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string
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default "3rdparty/blobs/soc/intel/quark/pdat.bin"
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depends on PLATFORM_USES_FSP1_1
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depends on ADD_FSP_PDAT_FILE
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help
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The path and filename of the Intel Galileo platform-data-patch (PDAT)
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binary. This binary file is generated by the platform-data-patch.py
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script released with the Quark BSP and contains the Ethernet address.
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config FSP_PDAT_LOC
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hex
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default 0xfff10000
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depends on PLATFORM_USES_FSP1_1
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depends on ADD_FSP_PDAT_FILE
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help
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The location in CBFS that the PDAT is located. It must match the
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PCD PcdPlatformDataBaseAddress of Quark SoC FSP.
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#####
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# RMU binary
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# The following options control the Quark chipset microcode file
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# placement in the flash image. This file is required to bring
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# the Quark processor out of reset.
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#####
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config ADD_RMU_FILE
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bool "Should the RMU binary be added to the flash image?"
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default n
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help
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The RMU file is required to get the chip out of reset.
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config RMU_FILE
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string
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default "3rdparty/blobs/soc/intel/quark/rmu.bin"
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depends on ADD_RMU_FILE
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help
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The path and filename of the Intel Quark RMU binary.
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config RMU_LOC
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hex
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default 0xfff00000
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depends on ADD_RMU_FILE
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help
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The location in CBFS that the RMU is located. It must match the
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strap-determined base address.
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#####
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# Bootblock
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# The following options support the C_ENVIRONMENT_BOOTBLOCK.
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#####
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config DCACHE_BSP_STACK_SIZE
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hex
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default 0x4000
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config C_ENV_BOOTBLOCK_SIZE
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hex
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default 0x8000
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endif # SOC_INTEL_QUARK
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