e39becf521
The implementation of udelay() with LAPIC timers existed first, as we did not have calculations implemented for TSC frequency. Change-Id: If510bcaadee67e3a5792b3fc7389353b672712f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34200 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
89 lines
2.3 KiB
Text
89 lines
2.3 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2009 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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config NORTHBRIDGE_INTEL_I945
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bool
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if NORTHBRIDGE_INTEL_I945
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config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
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def_bool y
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select HAVE_DEBUG_RAM_SETUP
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select VGA
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select INTEL_GMA_ACPI
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select INTEL_GMA_SSC_ALTERNATE_REF
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select INTEL_EDID
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select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
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select PARALLEL_MP
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config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
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def_bool n
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config NORTHBRIDGE_INTEL_SUBTYPE_I945GM
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def_bool n
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config BOOTBLOCK_NORTHBRIDGE_INIT
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string
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default "northbridge/intel/i945/bootblock.c"
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config VGA_BIOS_ID
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string
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default "8086,27a2" if NORTHBRIDGE_INTEL_SUBTYPE_I945GM
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default "8086,2772" if NORTHBRIDGE_INTEL_SUBTYPE_I945GC
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config I945_LVDS
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def_bool n
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
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help
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Selected by mainboards that use native graphics initialization
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for the LVDS port. A linear framebuffer is only supported for
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LVDS.
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config MMCONF_BASE_ADDRESS
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hex
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default 0xf0000000
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config OVERRIDE_CLOCK_DISABLE
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bool
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default n
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help
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Usually system firmware turns off system memory clock
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signals to unused SO-DIMM slots to reduce EMI and power
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consumption.
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However, some boards do not like unused clock signals to
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be disabled.
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config MAXIMUM_SUPPORTED_FREQUENCY
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int
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default 0
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help
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If non-zero, this designates the maximum DDR frequency
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the board supports, despite what the chipset should be
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capable of.
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config CHECK_SLFRCS_ON_RESUME
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def_bool n
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help
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On some boards it may be neccessary to hard reset early
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during resume from S3 if the SLFRCS register indicates that
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a memory channel is not guaranteed to be in self-refresh.
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On other boards the check always creates a false positive,
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effectively making it impossible to resume.
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config SMM_RESERVED_SIZE
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hex
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default 0x100000
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endif
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