Philipp Hug 199b75f58a arch/riscv: provide a monotonic timer ... The RISC-V Privileged Architecture specification defines the Machine Time Registers (mtime and mtimecmp) in section 3.1.15. Makes it possible to use the generic udelay. The timer is enabled using RISCV_USE_ARCH_TIMER for the lowrisc, sifive and ucb soc. Change-Id: I5139601226e6f89da69e302a10f2fb56b4b24f38 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27434 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2018-09-14 09:28:06 +00:00
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include/soc	soc/sifive/fu540: Initialize PLL and clock	2018-09-12 12:31:28 +00:00
bootblock.c
cbmem.c
clint.c	soc/sifive/fu540: add CLINT support	2018-09-10 15:03:37 +00:00
clock.c	soc/sifive/fu540: Get SDRAM controller out of reset	2018-09-13 15:33:57 +00:00
ddrregs.h	soc/sifive/fu540: add SiFive supplied header files for SDRAM initialization	2018-09-14 09:27:29 +00:00
Kconfig	arch/riscv: provide a monotonic timer	2018-09-14 09:28:06 +00:00
Makefile.inc	soc/sifive/fu540: Makefile: include mtime_init in ramstage	2018-09-10 20:36:45 +00:00
media.c
otp.c	soc/sifive: fix compiler warning	2018-09-10 20:37:17 +00:00
regconfig-ctl.h	soc/sifive/fu540: add SiFive supplied header files for SDRAM initialization	2018-09-14 09:27:29 +00:00
regconfig-phy.h	soc/sifive/fu540: add SiFive supplied header files for SDRAM initialization	2018-09-14 09:27:29 +00:00
sdram.c	sifive/fu540: add empty sdram init and size functions	2018-07-18 07:54:54 +00:00
uart.c	uart/sifive: make divisor configurable	2018-09-13 15:32:53 +00:00