933f90147b
These appear to be leftovers from old SMM relocation code. Change-Id: I689bee55943b29990f54cb798b999940eae180bc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
78 lines
1.6 KiB
C
78 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/device.h>
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#include <device/pci.h>
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#include <console/console.h>
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#include <arch/io.h>
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#include <cpu/intel/smm_reloc.h>
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#include <cpu/x86/smm.h>
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#include "pch.h"
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void smm_southbridge_clear_state(void)
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{
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u32 smi_en;
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/* Log events from chipset before clearing */
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if (CONFIG(ELOG))
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pch_log_state();
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printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
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printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", get_pmbase());
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smi_en = inl(get_pmbase() + SMI_EN);
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if (smi_en & APMC_EN) {
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printk(BIOS_INFO, "SMI# handler already enabled?\n");
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return;
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}
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printk(BIOS_DEBUG, "\n");
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/* Dump and clear status registers */
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clear_smi_status();
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clear_pm1_status();
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clear_tco_status();
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clear_gpe_status();
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}
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static void smm_southbridge_enable(uint16_t pm1_events)
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{
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printk(BIOS_DEBUG, "Enabling SMIs.\n");
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/* Configure events */
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enable_pm1(pm1_events);
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disable_gpe(PME_B0_EN);
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/* Enable SMI generation:
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* - on APMC writes (io 0xb2)
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* - on writes to SLP_EN (sleep states)
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* - on writes to GBL_RLS (bios commands)
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* No SMIs:
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* - on microcontroller writes (io 0x62/0x66)
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* - on TCO events
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*/
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enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
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}
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void global_smi_enable(void)
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{
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smm_southbridge_enable(PWRBTN_EN | GBL_EN);
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}
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void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
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{
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/*
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* Issue SMI to set the gnvs pointer in SMM.
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* tcg and smi1 are unused.
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*
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* EAX = APM_CNT_GNVS_UPDATE
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* EBX = gnvs pointer
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* EDX = APM_CNT
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*/
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asm volatile (
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"outb %%al, %%dx\n\t"
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: /* ignore result */
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: "a" (APM_CNT_GNVS_UPDATE),
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"b" ((u32)gnvs),
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"d" (APM_CNT)
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);
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}
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