03784fa97a
This patch adds a new static assertion macro that can be used to check the offsets in structures that overlay register sets at compile time. It uses the _Static_assert() declaration from the new ISO C11 standard, which is supported (even without -std=c11) by GCC after version 4.6. (There is supposedly also support in clang, although I haven't tried it... let's deal with compiler issues when/if they turn up.) I've added it to all structures for our current ARM SoCs for now, and I think every new register overlay we add going forward should use them (at least for the last member, but feel free to add more if you think it's useful). Change-Id: If32510e7049739ad05618d363a854dc372d64386 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179412 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit cef5fa13c31375a316ca4556c0039b17c8ea7900) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6905 Tested-by: build bot (Jenkins)
79 lines
2.5 KiB
C
79 lines
2.5 KiB
C
/*
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* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _TEGRA124_FLOW_H_
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#define _TEGRA124_FLOW_H_
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struct flow_ctlr {
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u32 halt_cpu_events; /* offset 0x00 */
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u32 halt_cop_events; /* offset 0x04 */
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u32 cpu_csr; /* offset 0x08 */
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u32 cop_csr; /* offset 0x0c */
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u32 xrq_events; /* offset 0x10 */
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u32 halt_cpu1_events; /* offset 0x14 */
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u32 cpu1_csr; /* offset 0x18 */
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u32 halt_cpu2_events; /* offset 0x1c */
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u32 cpu2_csr; /* offset 0x20 */
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u32 halt_cpu3_events; /* offset 0x24 */
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u32 cpu3_csr; /* offset 0x28 */
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u32 cluster_control; /* offset 0x2c */
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u32 halt_cop1_events; /* offset 0x30 */
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u32 halt_cop1_csr; /* offset 0x34 */
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u32 cpu_pwr_csr; /* offset 0x38 */
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u32 mpid; /* offset 0x3c */
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u32 ram_repair; /* offset 0x40 */
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};
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check_member(flow_ctlr, ram_repair, 0x40);
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enum {
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FLOW_MODE_SHIFT = 29,
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FLOW_MODE_MASK = 0x7 << FLOW_MODE_SHIFT,
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FLOW_MODE_NONE = 0 << FLOW_MODE_SHIFT,
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FLOW_MODE_RUN_AND_INT = 1 << FLOW_MODE_SHIFT,
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FLOW_MODE_WAITEVENT = 2 << FLOW_MODE_SHIFT,
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FLOW_MODE_WAITEVENT_AND_INT = 3 << FLOW_MODE_SHIFT,
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FLOW_MODE_STOP_UNTIL_IRQ = 4 << FLOW_MODE_SHIFT,
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FLOW_MODE_STOP_UNTIL_IRQ_AND_INT = 5 << FLOW_MODE_SHIFT,
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FLOW_MODE_STOP_UNTIL_EVENT_AND_IRQ = 6 << FLOW_MODE_SHIFT,
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};
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/* HALT_COP_EVENTS_0, 0x04 */
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enum {
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FLOW_EVENT_GIC_FIQ = 1 << 8,
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FLOW_EVENT_GIC_IRQ = 1 << 9,
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FLOW_EVENT_LIC_FIQ = 1 << 10,
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FLOW_EVENT_LIC_IRQ = 1 << 11,
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FLOW_EVENT_IBF = 1 << 12,
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FLOW_EVENT_IBE = 1 << 13,
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FLOW_EVENT_OBF = 1 << 14,
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FLOW_EVENT_OBE = 1 << 15,
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FLOW_EVENT_XRQ_A = 1 << 16,
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FLOW_EVENT_XRQ_B = 1 << 17,
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FLOW_EVENT_XRQ_C = 1 << 18,
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FLOW_EVENT_XRQ_D = 1 << 19,
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FLOW_EVENT_SMP30 = 1 << 20,
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FLOW_EVENT_SMP31 = 1 << 21,
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FLOW_EVENT_X_RDY = 1 << 22,
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FLOW_EVENT_SEC = 1 << 23,
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FLOW_EVENT_MSEC = 1 << 24,
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FLOW_EVENT_USEC = 1 << 25,
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FLOW_EVENT_X32K = 1 << 26,
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FLOW_EVENT_SCLK = 1 << 27,
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FLOW_EVENT_JTAG = 1 << 28
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};
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#endif /* _TEGRA124_FLOW_H_ */
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