dbc6fcd021
Also, add pretty printing of Westmere's DMI registers (tested on my t410s by staring at non-zero output values :) Apparently Nehalem does not have a MEMBAR? But there are some documented memory controller control registers in PCI configuration space... left out for now. The PCIEXBAR is not documented publicly AFAICT, but there is a similar register on a device on bus 0xFF. phcoder might know more... Change-Id: I5faadb6e4f701728f5290276c02809b4993bd86d Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/3505 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> |
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| .. | ||
| Makefile | ||
| amb.c | ||
| cpu.c | ||
| gpio.c | ||
| inteltool.8 | ||
| inteltool.c | ||
| inteltool.h | ||
| memory.c | ||
| pcie.c | ||
| powermgt.c | ||
| rootcmplx.c | ||