coreboot-kgpe-d16/src
Aaron Durbin 1ce0b3022c baytrail: allow downstream use of SSE instructions
If a payload is compiled to use SSE instructions it will
fault with an undefined opcode because SSE instructions weren't
enabled. Therefore enable SSE instructions at runtime.

BUG=chrome-os-partner:22991
BRANCH=None
TEST=Built and booted with SSE enabled payload. No exceptions seen.

Change-Id: I919c1ad319c6ce8befec5b4b1fd8c6343d51ccc1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172642
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4881
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-13 16:55:45 +01:00
..
arch SMP: Add arch-agnostic boot_cpu() 2014-02-11 21:55:30 +01:00
console Move hexdump32() to lib/hexdump. 2014-02-11 21:54:34 +01:00
cpu PCI: Drop includes under cpu 2014-02-12 21:57:11 +01:00
device PCI: Add capability list parser to romstage 2014-02-12 22:01:00 +01:00
drivers usbdebug: Split to USB host/device 2014-02-12 21:55:56 +01:00
ec chromeec: allow override of i8042 interrupt 2014-01-30 05:36:33 +01:00
include PCI: Add capability list parser to romstage 2014-02-12 22:01:00 +01:00
lib SMP: Add arch-agnostic boot_cpu() 2014-02-11 21:55:30 +01:00
mainboard google boards: Do not hardcode location of spd.bin 2014-02-12 23:37:24 +01:00
northbridge Eliminate some ASL warnings 2014-02-13 01:04:02 +01:00
soc baytrail: allow downstream use of SSE instructions 2014-02-13 16:55:45 +01:00
southbridge lynxpoint: Do not put SerialIO devices into D3Hot in ACPI mode 2014-02-12 23:31:19 +01:00
superio Eliminate some ASL warnings 2014-02-13 01:04:02 +01:00
vendorcode amd/cimx: fix sb(8|9)00 NULL type redefine 2014-02-11 22:23:15 +01:00
Kconfig Kconfig: Move vendorcode menu up from the bottom to above Chipset menu 2014-02-11 21:37:29 +01:00