efc40090f5
List of changes: 1. Initial code block to select SOC_INTEL_ALDERLAKE Kconfig 2. Add minimum code to make ADL-P RVP build successfully 3. Mainly bootblock and verstage code added to reach till verstage 4. Add support for 2 mainboards as ADL-P board with default EC (Windows SKU) and Chrome EC (Chrome SKU) 5. Add empty dsdt.asl to avoid compilation error TEST=Able to build and boot ADL-P RVP till romstage early. Change-Id: I2b551f48a4eb4d621d9a86c5d189c517d5610069 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
10 lines
214 B
C
10 lines
214 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <bootblock_common.h>
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void bootblock_mainboard_init(void)
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{
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variant_configure_early_gpio_pads();
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}
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