1db5bc7dac
- Reformat some lines of code - Put names to all used MCHBAR registers - Move MCHBAR registers into a separate file, for future expansion - Rewrite several comments - Use C-style comments for consistency - Rewrite some hex constants - Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0) Tested, it does not change the binary of Asrock B85M Pro4. Change-Id: I926289304acb834f9b13cd7902801798f8ee478a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38434 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
49 lines
1.8 KiB
C
49 lines
1.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/pci_ops.h>
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#include "haswell.h"
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void intel_northbridge_haswell_finalize_smm(void)
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{
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pci_or_config16(HOST_BRIDGE, 0x50, 1 << 0); /* GGC */
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pci_or_config32(HOST_BRIDGE, 0x5c, 1 << 0); /* DPR */
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pci_or_config32(HOST_BRIDGE, 0x78, 1 << 10); /* ME */
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pci_or_config32(HOST_BRIDGE, 0x90, 1 << 0); /* REMAPBASE */
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pci_or_config32(HOST_BRIDGE, 0x98, 1 << 0); /* REMAPLIMIT */
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pci_or_config32(HOST_BRIDGE, 0xa0, 1 << 0); /* TOM */
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pci_or_config32(HOST_BRIDGE, 0xa8, 1 << 0); /* TOUUD */
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pci_or_config32(HOST_BRIDGE, 0xb0, 1 << 0); /* BDSM */
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pci_or_config32(HOST_BRIDGE, 0xb4, 1 << 0); /* BGSM */
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pci_or_config32(HOST_BRIDGE, 0xb8, 1 << 0); /* TSEGMB */
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pci_or_config32(HOST_BRIDGE, 0xbc, 1 << 0); /* TOLUD */
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MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */
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MCHBAR32_OR(SAPMCTL, 1UL << 31); /* SA PM */
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MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */
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MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */
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MCHBAR32_OR(REQLIM, 1UL << 31);
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MCHBAR32_OR(DMIVCLIM, 1UL << 31);
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MCHBAR32_OR(CRDTLCK, 1 << 0);
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/* Memory Controller Lockdown */
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MCHBAR8(MC_LOCK) = 0x8f;
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/* Read+write the following */
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MCHBAR32(VDMBDFBARKVM) = MCHBAR32(VDMBDFBARKVM);
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MCHBAR32(VDMBDFBARPAVP) = MCHBAR32(VDMBDFBARPAVP);
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MCHBAR32(HDAUDRID) = MCHBAR32(HDAUDRID);
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}
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