coreboot-kgpe-d16/src/mainboard/google/veyron_mickey
Aaron Durbin 9796f60c62 coreboot: move TS_END_ROMSTAGE to one spot
While the romstage code flow is not consistent across all
mainboards/chipsets there is only one way of running ramstage
from romstage -- run_ramstage(). Move the
timestamp_add_now(TS_END_ROMSTAGE) to be within run_ramstage().

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados. TS_END_ROMSTAGE still present in
     timestamp table.

Change-Id: I4b584e274ce2107e83ca6425491fdc71a138e82c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11700
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-24 16:12:44 +00:00
..
sdram_inf veyron: add Nanya NT5CC256M16DP sdram 2015-08-28 06:45:03 +00:00
board.h google/veyron_mickey: Add new mainboard 2015-06-05 18:57:01 +02:00
boardid.c google/veyron_mickey: Add new mainboard 2015-06-05 18:57:01 +02:00
bootblock.c rk3288: Allow board-specific APLL (CPU clock) settings 2015-09-08 11:50:50 +00:00
chromeos.c veyron_mickey: Apply differences between Brain and Mickey 2015-06-23 08:21:23 +02:00
devicetree.cb veyron_*: Set vop_mode in devicetree.cb files 2015-07-06 09:40:23 +02:00
Kconfig ChromeOS mainboards: Move more Kconfig symbols under CHROMEOS 2015-08-26 15:45:36 +00:00
Kconfig.name veyron_mickey: Update board name to uppercase 2015-06-07 03:01:53 +02:00
mainboard.c veyron_mickey: Apply differences between Brain and Mickey 2015-06-23 08:21:23 +02:00
Makefile.inc google/veyron: Fix building with CHROMEOS enabled 2015-06-30 08:17:52 +02:00
memlayout.ld google/veyron_mickey: Add new mainboard 2015-06-05 18:57:01 +02:00
reset.c google/veyron_mickey: Add new mainboard 2015-06-05 18:57:01 +02:00
romstage.c coreboot: move TS_END_ROMSTAGE to one spot 2015-09-24 16:12:44 +00:00
sdram_configs.c veyron: add Nanya NT5CC256M16DP sdram 2015-08-28 06:45:03 +00:00