Julius Werner 94e2ec7253 arch: Retire cache_sync_instructions() from <arch/cache.h> (except arm) ... cache_sync_instructions() has been superseded by arch_program_segment_loaded() and friends for a while. There are no uses in common code anymore, so let's remove it from <arch/cache.h> for all architectures. arm64 still has an implementation and one reference, but they are not really needed since arch_program_segment_loaded() does the same thing already. Remove them. Leave it in arm(32) since there are several references (including in SoC code) that I don't feel like tracking down and testing right now. Change-Id: I6b776ad49782d981d6f1ef0a0e013812cf408524 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2018-08-07 20:55:58 +00:00
..
include	arch: Retire cache_sync_instructions() from <arch/cache.h> (except arm)	2018-08-07 20:55:58 +00:00
Kconfig	riscv: add support for modifying compiler options	2018-07-17 18:09:43 +00:00
Makefile.inc	riscv: remove redundancy in Makefile	2018-08-01 14:37:06 +00:00
boot.c	arch/riscv: Pass the bootrom-provided FDT to the payload	2018-02-20 20:46:12 +00:00
bootblock.S	riscv: add CAR interface	2018-07-18 18:56:10 +00:00
mcall.c	riscv: add include/arch/smp/ directory	2018-07-12 11:53:30 +00:00
misc.c	…
payload.S	arch/riscv: Pass the bootrom-provided FDT to the payload	2018-02-20 20:46:12 +00:00
stages.c	arch/riscv: Pass the bootrom-provided FDT to the payload	2018-02-20 20:46:12 +00:00
tables.c	lib: add common write_tables() implementation	2016-04-21 20:49:05 +02:00
trap_handler.c	arch/riscv: Update encoding.h and adjust related code	2018-02-20 20:46:39 +00:00
trap_util.S	arch/riscv: Align trap_entry to 4 bytes, as required by spec	2018-02-20 20:44:43 +00:00
virtual_memory.c	arch/riscv: Delegate the page fault exceptions	2018-02-20 20:46:53 +00:00