coreboot-kgpe-d16/src
Duncan Laurie 1f52f51f4e baytrail: Add function to read top of low memory
The top of low memory is also the start of the region where
PCIe resources are allocated.  This needs to be passed in
ACPI but is only readable from IOSF.

BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi

Change-Id: Iad95335f72dc3e35b837bedb8d52d388c861a330
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175625
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4935
Tested-by: build bot (Jenkins)
2014-04-30 23:11:21 +02:00
..
arch uart: Support multiple ports 2014-04-30 06:59:05 +02:00
console console: Drop EARLY_CONSOLE option 2014-04-30 07:00:20 +02:00
cpu console: Move UART port defaults to mainboard 2014-04-30 07:00:43 +02:00
device OxPCIe uart: Split PCI bridge control 2014-04-09 11:29:45 +02:00
drivers console: Drop EARLY_CONSOLE option 2014-04-30 07:00:20 +02:00
ec ec/compal/ene932: Update to use coreboot EC-mainboard API 2014-04-19 03:49:48 +02:00
include console: Drop EARLY_CONSOLE option 2014-04-30 07:00:20 +02:00
lib Rename coreboot_ram stage to ramstage 2014-04-26 13:27:09 +02:00
mainboard baytrail: Add reserved MMIO regions to ACPI 2014-04-30 23:11:11 +02:00
northbridge Rename coreboot_ram stage to ramstage 2014-04-26 13:27:09 +02:00
soc baytrail: Add function to read top of low memory 2014-04-30 23:11:21 +02:00
southbridge AGESA SPI: Fix Kconfig options 2014-04-29 17:31:40 +02:00
superio superio/winbond/w83627ehg: Convert romstage to generic component 2014-04-28 20:14:58 +02:00
vendorcode vendorcode/amd/agesa/fam14: Build as a static library 2014-04-15 17:23:37 +02:00
Kconfig Rename coreboot_ram stage to ramstage 2014-04-26 13:27:09 +02:00