1fa72d5fe1
The min86 example SoC code along with the example mainboard should serve as a minimal example how a buildable x86 SoC code base can look like. This can serve, for instance, as a basis to add new SoCs to coreboot. Starting with a buildable commit should help with the review of the actual code, and also avoid any regressions when common coreboot code changes. As the example code itself is build-tested, it should advance with coreboot and can't rot like documentation might. It also serves as a check what APIs need to be implemented with the default Kconfig settings. Change-Id: Id76ab15fe77ae3e405c43f9c8677694f178be112 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45710 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
25 lines
675 B
Text
25 lines
675 B
Text
config SOC_EXAMPLE_MIN86
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bool
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help
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This example SoC code along with the example/min86 mainboard
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should serve as a minimal example how a buildable x86 SoC code
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base can look like.
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This can serve, for instance, as a basis to add new SoCs to
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coreboot. Starting with a buildable commit should help with
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the review of the actual code, and also avoid any regressions
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when common coreboot code changes.
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if SOC_EXAMPLE_MIN86
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config SOC_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_ALL_STAGES_X86_32
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select NO_MONOTONIC_TIMER
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select NO_MMCONF_SUPPORT
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select UNKNOWN_TSC_RATE
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config DCACHE_BSP_STACK_SIZE # required by arch/x86/car.ld
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default 0x100
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endif
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