x86: Add a minimal example SoC along with a board

The min86 example SoC code along with the example mainboard
should serve as a minimal example how a buildable x86 SoC code
base can look like.

This can serve, for instance, as a basis to add new SoCs to
coreboot. Starting with a buildable commit should help with
the review of the actual code, and also avoid any regressions
when common coreboot code changes.

As the example code itself is build-tested, it should advance
with coreboot and can't rot like documentation might. It also
serves as a check what APIs need to be implemented with the
default Kconfig settings.

Change-Id: Id76ab15fe77ae3e405c43f9c8677694f178be112
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45710
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/example/Kconfig

@@ -0,0 +1,15 @@
+if VENDOR_EXAMPLE
+
+choice
+	prompt "Mainboard model"
+
+source "src/mainboard/example/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/example/*/Kconfig"
+
+config MAINBOARD_VENDOR
+	default "Example"
+
+endif # VENDOR_EXAMPLE

src/mainboard/example/Kconfig.name

@@ -0,0 +1,2 @@
+config VENDOR_EXAMPLE
+	bool "Example boards"

src/mainboard/example/min86/Kconfig

@@ -0,0 +1,14 @@
+if BOARD_EXAMPLE_MIN86
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select SOC_EXAMPLE_MIN86
+	select MISSING_BOARD_RESET
+
+config MAINBOARD_DIR
+	default "example/min86"
+
+config MAINBOARD_PART_NUMBER
+	default "Min86"
+
+endif

src/mainboard/example/min86/Kconfig.name

@@ -0,0 +1,11 @@
+config BOARD_EXAMPLE_MIN86
+	bool "Minimal x86 fake board"
+	help
+	  This example mainboard code along with the example/min86 SoC
+	  should serve as a minimal example how a buildable x86 SoC code
+	  base can look like.
+
+	  This can serve, for instance, as a basis to add new SoCs to
+	  coreboot. Starting with a buildable commit should help with
+	  the review of the actual code, and also avoid any regressions
+	  when common coreboot code changes.

src/mainboard/example/min86/board_info.txt

@@ -0,0 +1 @@
+Category: misc

src/mainboard/example/min86/devicetree.cb

@@ -0,0 +1,6 @@
+chip soc/example/min86
+
+	device domain 0 on
+	end
+
+end

src/soc/example/Kconfig

@@ -0,0 +1 @@
+source "src/soc/example/*/Kconfig"

src/soc/example/min86/Kconfig

@@ -0,0 +1,25 @@
+config SOC_EXAMPLE_MIN86
+	bool
+	help
+	  This example SoC code along with the example/min86 mainboard
+	  should serve as a minimal example how a buildable x86 SoC code
+	  base can look like.
+
+	  This can serve, for instance, as a basis to add new SoCs to
+	  coreboot. Starting with a buildable commit should help with
+	  the review of the actual code, and also avoid any regressions
+	  when common coreboot code changes.
+
+if SOC_EXAMPLE_MIN86
+
+config SOC_SPECIFIC_OPTIONS
+	def_bool y
+	select ARCH_ALL_STAGES_X86_32
+	select NO_MONOTONIC_TIMER
+	select NO_MMCONF_SUPPORT
+	select UNKNOWN_TSC_RATE
+
+config DCACHE_BSP_STACK_SIZE		# required by arch/x86/car.ld
+	default 0x100
+
+endif

src/soc/example/min86/Makefile.inc

@@ -0,0 +1,15 @@
+ifeq ($(CONFIG_SOC_EXAMPLE_MIN86),y)
+
+bootblock-y	+= cache_as_ram.S
+bootblock-y	+= ../../../cpu/intel/car/bootblock.c
+
+postcar-y	+= exit_car.S
+
+romstage-y	+= romstage.c
+
+ramstage-y	+= chip.c
+ramstage-y	+= timer.c
+
+subdirs-y	+= ../../../cpu/x86/mtrr
+
+endif

src/soc/example/min86/cache_as_ram.S

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+.global bootblock_pre_c_entry
+
+.code32
+bootblock_pre_c_entry:
+	call	bootblock_c_entry_bist
+
+.Lhlt:
+	hlt
+	jmp	.Lhlt

src/soc/example/min86/chip.c

@@ -0,0 +1,3 @@
+#include <device/device.h>
+
+struct chip_operations soc_example_min86_ops = { NULL };

src/soc/example/min86/exit_car.S

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+.global chipset_teardown_car
+
+.code32
+chipset_teardown_car:
+	/* Return to caller. */
+	jmp	*%esp

src/soc/example/min86/romstage.c

@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/cpu.h>
+
+asmlinkage void car_stage_entry(void)
+{
+}

src/soc/example/min86/timer.c

@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <delay.h>
+
+void init_timer(void)
+{
+}