2a6a79c706
The sta_himax83102 panel sometimes shows abnormally flickering horizontal lines. The front gate output will precharge the X point of the next pole circuit before TP term starts, and wait until the end of the TP term to resume the CLK. For this reason, the X point must be maintained during the TP term. In abnormal case, we measured a slight leakage at point X. This is because during the TP term, the GPW does not fully pull the VGL low, causing the TFT to not be closed tightly. To fix this, we completely pull GPW to VGL before entering the TP term. This will ensure that the TFT is closed tightly and prevent the abnormal display. BUG=b:299249186 BRANCH=corsola TEST=FW Screen display normally Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I5dddaaa38917a65990c1474b657db5eb551940b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77692 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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| .. | ||
| Kconfig | ||
| Makefile.inc | ||
| panel-AUO_B101UAN08_3.c | ||
| panel-AUO_KD101N80_45NA.c | ||
| panel-AUO_NT51021D8P.c | ||
| panel-BOE_TV080WUM_NG0.c | ||
| panel-BOE_TV101WUM_N53.c | ||
| panel-BOE_TV101WUM_NG0.c | ||
| panel-BOE_TV101WUM_NL6.c | ||
| panel-BOE_TV105WUM_NW0.c | ||
| panel-BOE_TV110C9M_LL0.c | ||
| panel-CMN_P097PFG_SSD2858.c | ||
| panel-INX_HJ110IZ_01A_B2.c | ||
| panel-INX_OTA7290D10P.c | ||
| panel-STA_2081101QFH032011_53G.c | ||
| panel-STA_HIMAX83102_J02.c | ||
| panel-STA_ILI9882T.c | ||
| panel-VIS_RM69299.c | ||
| panel.c | ||