Wisley Chen 21fb05606f mb/google/bry/anahera{4es}: Disable TCSS port1 ... Disable unused TCSS Port1. BUG=b:223082190 TEST=Build Change-Id: I63f4b7d89a1e37a00c58201ecc88bb336d0932c9 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>		2022-03-09 14:23:25 +00:00
..
acpi	coreboot_tables.c: Expose the ACPI RSDP	2022-03-09 14:21:01 +00:00
arch	timestamps: Rename timestamps to make names more consistent	2022-03-08 16:06:33 +00:00
commonlib	coreboot_tables.c: Expose the ACPI RSDP	2022-03-09 14:21:01 +00:00
console	console: Fix LOG_FAST macro	2022-02-22 23:13:50 +00:00
cpu	timestamps: Rename timestamps to make names more consistent	2022-03-08 16:06:33 +00:00
device	src: Make PCI ID define names shorter	2022-03-07 08:32:09 +00:00
drivers	{drivers/security}: Replace cb_err_t with enum cb_err	2022-03-09 08:40:43 +00:00
ec	ec/starlabs: Correct Keyboard Backlight offsets for GLK	2022-03-09 14:18:59 +00:00
include	coreboot_tables.c: Expose the ACPI RSDP	2022-03-09 14:21:01 +00:00
lib	coreboot_tables.c: Expose the ACPI RSDP	2022-03-09 14:21:01 +00:00
mainboard	mb/google/bry/anahera{4es}: Disable TCSS port1	2022-03-09 14:23:25 +00:00
northbridge	timestamps: Rename timestamps to make names more consistent	2022-03-08 16:06:33 +00:00
security	{drivers/security}: Replace cb_err_t with enum cb_err	2022-03-09 08:40:43 +00:00
soc	soc/intel/common: Add Kconfig to enable compression on ME_RW blobs	2022-03-09 14:21:57 +00:00
southbridge	timestamps: Rename timestamps to make names more consistent	2022-03-08 16:06:33 +00:00
superio	Use the fallthrough statement in switch loops	2022-02-16 21:29:53 +00:00
vendorcode	timestamps: Rename timestamps to make names more consistent	2022-03-08 16:06:33 +00:00
Kconfig	src/Kconfig: Update the path to 'c_start.S' for GDB_STUB config	2022-02-22 20:49:10 +00:00