321111774c
Add SPI driver code for the SPI flash controller, including both fast_spi and generic_spi. Change-Id: Ie45146721f39d3cec20ff5136adf8925c75da1cd Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.corp-partner.google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
43 lines
1.1 KiB
Makefile
43 lines
1.1 KiB
Makefile
ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y)
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subdirs-y += romstage
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subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/x86/mtrr
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subdirs-y += ../../../cpu/x86/tsc
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bootblock-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
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bootblock-y += bootblock/bootblock.c
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bootblock-y += bootblock/cpu.c
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bootblock-y += bootblock/pch.c
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bootblock-y += bootblock/report_platform.c
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bootblock-y += gpio.c
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bootblock-y += gspi.c
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bootblock-y += memmap.c
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bootblock-y += spi.c
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bootblock-$(CONFIG_UART_DEBUG) += uart.c
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romstage-y += gspi.c
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romstage-y += memmap.c
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romstage-y += reset.c
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romstage-y += spi.c
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romstage-$(CONFIG_UART_DEBUG) += uart.c
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ramstage-y += chip.c
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ramstage-y += gspi.c
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ramstage-y += memmap.c
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ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
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ramstage-y += spi.c
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ramstage-y += systemagent.c
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ramstage-$(CONFIG_UART_DEBUG) += uart.c
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postcar-y += memmap.c
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postcar-y += spi.c
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postcar-$(CONFIG_UART_DEBUG) += uart.c
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CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include/fsp20
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CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cannonlake
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CPPFLAGS_common += -I$(src)/soc/intel/cannonlake
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CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include
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endif
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