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instead of coreboot.strip. That fixes the normal image because the calculations for its offset in the ROM match reality again. This requires changes in CBFS configurations to minimize the bootblock size. These are also done for CBFS boards. Other than this a couple of minor fixes are in this patch: - make asus/m2v-mx_se build with abuild with a crosscompiler - move CONFIG_CBFS for hp/dl145_g3 to Options.lb as it's done everywhere else - change the default config of abuild to not provide ROM_IMAGE_SIZE values for the images in a CBFS configuration - change abuild's crosscompile autodetection to not try to use "i386-elf-i386-elf-gcc" (which is bogus) Except for the latter two abuild changes (both in util/abuild/abuild), they're available as patch set on the mailing list in a mail from 2009-06-05 titled [PATCH]es to get normal image to work again with CBFS The changes in util/abuild/abuild are trivial and abuild tested. As discussed on the list, targets/hp/dl145_g3/Config-abuild.lb is deleted, now that Config.lb works again. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
52 lines
1.6 KiB
Text
52 lines
1.6 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License v2 as published by
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## the Free Software Foundation.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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target asus_m2v-mx_se
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mainboard asus/m2v-mx_se
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option CC="CROSSCC"
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option CROSS_COMPILE="CROSS_PREFIX"
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option HOSTCC="CROSS_HOSTCC"
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## ROM_SIZE is the total number of bytes allocated for coreboot use
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## (normal AND fallback images and payloads).
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# The board comes with 512KB SPI flash (DIP8), 128KB is for coreboot binary
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# 384KB of flash is for payload/roms.
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option ROM_SIZE = 512 * 1024
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## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
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## not including any payload.
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# Please note that 128KB is cached for (XIP) too
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option ROM_IMAGE_SIZE = 128 * 1024
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## FALLBACK_SIZE is the amount of the ROM the complete fallback image
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## (including payload) will use.
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option FALLBACK_SIZE = ROM_SIZE
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romimage "fallback"
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option USE_FALLBACK_IMAGE=1
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payload __PAYLOAD__
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end
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buildrom ./coreboot.rom ROM_SIZE "fallback"
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