25fc070e35
Setting the clock source depends on clock request pin for WLAN/SD/SSD device. Also turn off the unused (4/5/6) clock sources. In guybrush, clock source 0/1/2/3 are routed for WLAN/SD/WWAN/SSD device. BUG=b:186384256 BRANCH=none TEST=Verify the config setting can update to the GPPCLKCONTROL registers. Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Change-Id: I240543e92cbc178cee034c37d7c26da0a6bbb7f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56895 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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| .. | ||
| spd | ||
| variants | ||
| board_info.txt | ||
| bootblock.c | ||
| chromeos.c | ||
| chromeos.fmd | ||
| dsdt.asl | ||
| ec.c | ||
| Kconfig | ||
| Kconfig.name | ||
| mainboard.c | ||
| Makefile.inc | ||
| port_descriptors.c | ||
| romstage.c | ||
| smihandler.c | ||
| verstage.c | ||