coreboot-kgpe-d16/src
Patrick Rudolph 9f3f9154c9 nb/intel/sandybridge/romstage: Read fuse bits for max MEM Clk
Instead of hardcoding the maximum supported DDR frequency to
800Mhz (DDR3-1600), read the fuse bits that encode this information.

Test system:
 * Intel IvyBridge
 * Gigabyte GA-B75M-D3H

Change-Id: I515a2695a490f16aeb946bfaf3a1e860c607cba9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13487
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-02 21:46:49 +01:00
..
acpi acpi/: add missing license header 2016-01-14 22:52:11 +01:00
arch src/arch/x86/smbios: Add vendors 2016-03-02 21:39:15 +01:00
commonlib cbfs: Fix compiler error for gcc versions < 4.6 2016-02-25 06:17:52 +01:00
console console: Add higher baud rates 2016-02-22 02:39:07 +01:00
cpu tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))" 2016-02-26 07:01:21 +01:00
device nb/intel/sandybridge/raminit: Add XMP support 2016-02-20 05:11:37 +01:00
drivers During DRAM initialization on certain ASpeed devices, an incorrect 2016-02-26 20:05:16 +01:00
ec ASL: Remove unused modulo recipient. 2016-02-09 22:56:00 +01:00
include nb/intel/sandybridge/romstage: Read fuse bits for max MEM Clk 2016-03-02 21:46:49 +01:00
lib lib/bootblock: provide SoC callback parity with mainboard 2016-02-26 02:16:14 +01:00
mainboard Skylake boards: Enabling HWP (hardware P state control) 2016-03-01 20:54:34 +01:00
northbridge nb/intel/sandybridge/romstage: Read fuse bits for max MEM Clk 2016-03-02 21:46:49 +01:00
soc Skylake: Support Intel Speed Shift Technology based on config 2016-03-01 20:57:45 +01:00
southbridge southbridge/intel/ibexpeak: Use common gpio.c 2016-02-23 00:28:26 +01:00
superio superio/nuvoton/nct5572d: Add PS/2 presence detect 2016-02-09 20:34:15 +01:00
vendorcode vboot: Set S3_RESUME flag for vboot context if necessary 2016-02-29 20:18:33 +01:00
Kconfig cbfs: Add LZ4 in-place decompression support for pre-RAM stages 2016-02-22 21:38:37 +01:00