Aaron Durbin 27d153cabc skylake: re-enable PCIe L1 sub states ... All boards should have their L1 sub states working now so re-enable the defaults. BUG=chrome-os-partner:41861 BRANCH=None TEST=Built and booted glados into OS. PCIe devices show up still. Change-Id: Ic040fa108a662e15bb97cf8b0961f0f56683e146 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 380491f8267e60c3c6bc62486aaf21e201fcfd36 Original-Change-Id: Idc6923b1fdd1c20d463eb7782be112f90b9adbfd Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285170 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/10989 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2015-07-21 20:07:03 +02:00
..
acpi	skylake: remove whitespace from ASL files	2015-07-17 21:37:32 +02:00
bootblock
include/soc
microcode	soc/intel: Remove microcode terminators	2015-07-17 23:05:17 +02:00
romstage	skylake: honor pcie root port settings already in chip.h	2015-07-21 20:05:50 +02:00
acpi.c
chip.c
chip.h	skylake: Show SPI controller if enabled in devicetree.cb	2015-07-21 20:05:26 +02:00
cpu.c
cpu_info.c
elog.c
finalize.c
flash_controller.c
gpio.c
igd.c
Kconfig	skylake: re-enable PCIe L1 sub states	2015-07-21 20:07:03 +02:00
lpc.c
Makefile.inc
memmap.c
monotonic_timer.c
pch.c
pcie.c
pcr.c
pei_data.c
pmc.c
pmutil.c
ramstage.c
smbus.c
smbus_common.c
smi.c
smihandler.c
smmrelocate.c
systemagent.c
tsc_freq.c
uart.c
xhci.c