d8214d7e0e
SoCs from Skylake on have many settings as so called private con- figuration registers (PCRs). These are organized as 256 ports with a 64KiB space each. We use the Primary to Sideband (P2SB) bridge's BAR to access them. Change-Id: Iede4ac601355e2be377bc986d62d20098980ec35 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19593 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
32 lines
949 B
C
32 lines
949 B
C
/*
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* inteltool - dump all registers on an Intel CPU + chipset based system.
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*
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* Copyright (C) 2017 secunet Security Networks AG
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef INTELTOOL_PCR_H
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#define INTELTOOL_PCR_H 1
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#include <stdint.h>
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#include "inteltool.h"
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#define SBBAR_SIZE (16 * MiB)
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#define PCR_PORT_SIZE (64 * KiB)
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uint32_t read_pcr32(uint8_t port, uint16_t offset);
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void print_pcr_ports(struct pci_dev *sb, const uint8_t *ports, size_t count);
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void pcr_init(struct pci_dev *sb);
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void pcr_cleanup(void);
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#endif
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