ff0d8698c2
This adds a struct for registers along with some bits from ATF to the generic PL011 driver. It also adds a naive implementation of uart_tx_flush() which was previously stubbed out. Change-Id: Iee3fc6308cb92ad784e5ff3ac3a6e995d535be65 Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/23031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
94 lines
3 KiB
C
94 lines
3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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* Copyright 2018-present Facebook, Inc.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __DRIVERS_UART_PL011_H
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#define __DRIVERS_UART_PL011_H
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#include <inttypes.h>
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#include <types.h>
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/* PL011 r1p5 registers */
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struct pl011_uart {
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u32 dr;
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u32 rsr_ecr;
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u8 rsvd1[0x10];
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u32 fr;
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u8 rsvd2[0x4];
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u32 ilpr;
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u32 ibrd;
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u32 fbrd;
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u32 lcr_h;
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u32 cr;
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u32 ifls;
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u32 imsc;
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u32 ris;
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u32 mis;
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u32 icr;
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u32 dmacr;
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u8 rsvd3[0xf94];
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u32 periphid0;
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u32 periphid1;
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u32 periphid2;
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u32 periphid3;
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u32 cellid0;
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u32 cellid1;
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u32 cellid2;
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u32 cellid3;
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};
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check_member(pl011_uart, cellid3, 0xffc);
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/*************************************************************************/
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/* Bit definitions from arm-trusted-firmware/include/drivers/arm/pl011.h */
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/*************************************************************************/
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/* Flag reg bits */
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#define PL011_UARTFR_RI (1 << 8) /* Ring indicator */
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#define PL011_UARTFR_TXFE (1 << 7) /* Transmit FIFO empty */
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#define PL011_UARTFR_RXFF (1 << 6) /* Receive FIFO full */
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#define PL011_UARTFR_TXFF (1 << 5) /* Transmit FIFO full */
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#define PL011_UARTFR_RXFE (1 << 4) /* Receive FIFO empty */
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#define PL011_UARTFR_BUSY (1 << 3) /* UART busy */
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#define PL011_UARTFR_DCD (1 << 2) /* Data carrier detect */
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#define PL011_UARTFR_DSR (1 << 1) /* Data set ready */
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#define PL011_UARTFR_CTS (1 << 0) /* Clear to send */
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#define PL011_UARTFR_TXFF_BIT 5 /* Transmit FIFO full bit in
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UARTFR register */
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#define PL011_UARTFR_RXFE_BIT 4 /* Receive FIFO empty bit in
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UARTFR register */
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#define PL011_UARTFR_BUSY_BIT 3 /* UART busy bit in UARTFR
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register */
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/* Control reg bits */
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#define PL011_UARTCR_CTSEN (1 << 15) /* CTS hardware flow control
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enable */
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#define PL011_UARTCR_RTSEN (1 << 14) /* RTS hardware flow control
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enable */
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#define PL011_UARTCR_RTS (1 << 11) /* Request to send */
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#define PL011_UARTCR_DTR (1 << 10) /* Data transmit ready. */
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#define PL011_UARTCR_RXE (1 << 9) /* Receive enable */
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#define PL011_UARTCR_TXE (1 << 8) /* Transmit enable */
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#define PL011_UARTCR_LBE (1 << 7) /* Loopback enable */
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#define PL011_UARTCR_UARTEN (1 << 0) /* UART Enable */
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/* FIFO Enabled / No Parity / 8 Data bit / One Stop Bit */
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#define PL011_LINE_CONTROL (PL011_UARTLCR_H_FEN | PL011_UARTLCR_H_WLEN_8)
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/* Line Control Register Bits */
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#define PL011_UARTLCR_H_SPS (1 << 7) /* Stick parity select */
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#define PL011_UARTLCR_H_WLEN_8 (3 << 5)
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#define PL011_UARTLCR_H_WLEN_7 (2 << 5)
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#define PL011_UARTLCR_H_WLEN_6 (1 << 5)
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#define PL011_UARTLCR_H_WLEN_5 (0 << 5)
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#define PL011_UARTLCR_H_FEN (1 << 4) /* FIFOs Enable */
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#define PL011_UARTLCR_H_STP2 (1 << 3) /* Two stop bits select */
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#define PL011_UARTLCR_H_EPS (1 << 2) /* Even parity select */
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#define PL011_UARTLCR_H_PEN (1 << 1) /* Parity Enable */
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#define PL011_UARTLCR_H_BRK (1 << 0) /* Send break */
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#endif /* ! __DRIVERS_UART_PL011_H */
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