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Arthur Heymans 2a4aadab70 mb/intel/dg43gt: Add mainboard
This mainboard features is an G43 northbridge, ICH10 southbridge and
Winbond W83627dhg SuperI/O. This board is impossible to flash
internally with vendor bios (BIOS region is WP and other regions like
IFD and ME are read only and inaccessible respectively). Due to either
ICH10 or board layout it is also impossible to do ISP, which requires
desoldering flash chip. To make hacking more easy there is an empty
SPI header next to spi flash pads which can be hooked up to a SPI
flash.

What works:
* 2 DDR2 dimms per channel (tested with 1+2G in CH0 and 2+2G in CH1);
* SATA with AHCI
* Integrated GPU with option rom (extracted from a Gigabyte vendor
  bios)
* VGA (on DVI) with NGI if patched to use DVI gmbus port for output
* PCI
* Reboot and S3 resume
* Descriptor mode with ME disable straps and ME region absent (no
  working gbe in this configuration though)
* USB.

What does not work:
* GBE (probably requires working ME);
* Analog on DVI port out is shaking, which is not the case with vendor
  BIOS (setting clockgen on smbus 0x69 like vendor fixes it).
* Booting with ME enabled (needs raminit patches for that)

Not tested:
* Sound;
* All the rest.

Not coreboot related problems:
* Flashing this board with vendor bios is a PITA and requires
  desoldering flash chip;
* In situ programming is not possible.

TESTED with SeaBIOS and Linux 4.10.8

Change-Id: If27280feb7cbf0a88f19fe6a63b1f6dbcf9b60f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-10 16:00:55 +00:00
3rdparty Update vboot submodule to upstream master 2017-07-31 20:30:55 +00:00
configs configs: Add intel/galileo test configurations 2017-06-20 18:10:47 +02:00
Documentation Documentation: Create Lesson2.md 2017-08-01 23:01:08 +00:00
payloads payloads/external/tianocore: build UEFI payload 2017-08-10 15:54:08 +00:00
src mb/intel/dg43gt: Add mainboard 2017-08-10 16:00:55 +00:00
util util/lint: Update license header lint scripts 2017-08-10 15:53:17 +00:00
.checkpatch.conf Fix files with multiple newlines at the end. 2017-07-24 15:08:08 +00:00
.clang-format Provide coreboot coding style formalisation file for clang-format 2015-11-10 00:49:03 +01:00
.gitignore payloads/external/tianocore: build UEFI payload 2017-08-10 15:54:08 +00:00
.gitmodules Set up 3rdparty/libgfxinit 2016-10-29 01:35:03 +02:00
.gitreview add .gitreview 2012-11-01 23:13:39 +01:00
COPYING update license template. 2006-08-12 22:03:36 +00:00
gnat.adc gnat.adc: Do not generate assertion code for Refined_Post 2016-10-29 01:33:31 +02:00
MAINTAINERS MAINTAINERS: Update support list 2017-07-15 21:53:21 +00:00
Makefile Makefile: update clean-utils & distclean-utils 2017-07-08 19:02:26 +00:00
Makefile.inc drivers/pc80/rtc: Build for bootblock and postcar stages too 2017-07-26 19:14:16 +00:00
README README: Update requirements 2017-06-27 17:04:32 +00:00
toolchain.inc toolchain.inc: Use -Wstack-usage only on gcc 2017-06-19 22:17:01 +02:00

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * https://www.coreboot.org/Supported_Motherboards
 * https://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * make
 * gcc / g++
   Because Linux distribution compilers tend to use lots of patches. coreboot
   does lots of "unusual" things in its build system, some of which break due
   to those patches, sometimes by gcc aborting, sometimes - and that's worse -
   by generating broken object code.
   Two options: use our toolchain (eg. make crosstools-i386) or enable the
   ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this
   case).
 * iasl (for targets with ACPI support)
 * pkg-config
 * libssl-dev (openssl)

Optional:

 * doxygen (for generating/viewing documentation)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig' and 'make nconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult https://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  https://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.