4ed9f9a507
This patch removes all redundant reset code block from each SoC and make use of common reset code block(fsp_reset.c) based on SOC_INTEL_COMMON_FSP_RESET. Respective SoC Kconfig to choose correct FSP global reset type as per FSP integration guide. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I71531f4cf7a40efa9ec55c48c2cb4fb6ea90531f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
30 lines
691 B
C
30 lines
691 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <cf9_reset.h>
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#include <intelblocks/pmclib.h>
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#include <soc/intel/common/reset.h>
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#include <soc/me.h>
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#include <soc/pm.h>
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static void do_force_global_reset(void)
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{
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/*
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* BIOS should ensure it does a global reset
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* to reset both host and Intel ME by setting
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* PCH PMC [B0:D31:F2 register offset 0xAC bit 20]
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*/
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pmc_global_reset_enable(true);
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/* Now BIOS can write 0x06 or 0x0E to 0xCF9 port
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* to global reset platform */
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do_full_reset();
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}
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void do_global_reset(void)
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{
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if (!send_global_reset()) {
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/* If ME unable to reset platform then
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* force global reset using PMC CF9GR register*/
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do_force_global_reset();
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}
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}
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