b794a69ce9
Add a new Kconfig option to ignore memory fuses that limit the maximum DRAM frequency to be used. The option is disabled by default and should only enabled by experienced users as it might decrease system stability or prevent a successful RAM training. Remove conflicting devicetree settings. Change-Id: I35dd78a02bcaafce8ba522d253c795d7835bacae Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nicola Corna <nicola@corna.info>
175 lines
4.8 KiB
Text
175 lines
4.8 KiB
Text
chip northbridge/intel/sandybridge
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register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
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register "gfx.link_frequency_270_mhz" = "0"
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register "gfx.ndid" = "3"
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register "gfx.use_spread_spectrum_clock" = "0"
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register "gpu_cpu_backlight" = "0x00000000"
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register "gpu_dp_b_hotplug" = "0"
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register "gpu_dp_c_hotplug" = "0"
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register "gpu_dp_d_hotplug" = "0"
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register "gpu_panel_port_select" = "0"
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register "gpu_panel_power_backlight_off_delay" = "0"
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register "gpu_panel_power_backlight_on_delay" = "0"
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register "gpu_panel_power_cycle_delay" = "0"
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register "gpu_panel_power_down_delay" = "0"
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register "gpu_panel_power_up_delay" = "0"
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register "gpu_pch_backlight" = "0x00000000"
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device cpu_cluster 0x0 on
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chip cpu/intel/socket_rPGA989
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device lapic 0x0 on
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end
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end
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chip cpu/intel/model_206ax
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register "c1_acpower" = "1"
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register "c1_battery" = "1"
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register "c2_acpower" = "3"
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register "c2_battery" = "3"
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register "c3_acpower" = "5"
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register "c3_battery" = "5"
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device lapic 0xacac off
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end
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end
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end
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device domain 0x0 on
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device pci 00.0 on # Host bridge Host bridge
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subsystemid 0x17aa 0x21dd
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end
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device pci 01.0 on # PCIe Bridge for discrete graphics
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end
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device pci 02.0 on # Internal graphics VGA controller
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subsystemid 0x17aa 0x21dd
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end
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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register "c2_latency" = "0x0065"
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register "docking_supported" = "1"
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register "gen1_dec" = "0x007c1611"
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register "gen2_dec" = "0x00040069"
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register "gen3_dec" = "0x000c0701"
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register "gen4_dec" = "0x00000000"
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register "gpi13_routing" = "2"
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register "gpi6_routing" = "2"
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register "p_cnt_throttling_supported" = "1"
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register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 1, 0, 0, 0 }"
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register "pcie_port_coalesce" = "1"
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register "sata_interface_speed_support" = "0x3"
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register "sata_port_map" = "0x3b"
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register "spi_uvscc" = "0"
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register "spi_lvscc" = "0x2005"
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device pci 16.0 on # Management Engine Interface 1
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subsystemid 0x17aa 0x21dd
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end
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device pci 16.1 off # Management Engine Interface 2
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end
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device pci 16.2 off # Management Engine IDE-R
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end
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device pci 16.3 off # Management Engine KT
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end
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device pci 19.0 off # Intel Gigabit Ethernet
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end
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device pci 1a.0 on # USB2 EHCI #2
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subsystemid 0x17aa 0x21dd
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end
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device pci 1b.0 on # High Definition Audio Audio controller
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subsystemid 0x17aa 0x21dd
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end
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device pci 1c.0 on # PCIe Port #1
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subsystemid 0x17aa 0x21dd
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end
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device pci 1c.1 on # PCIe Port #2
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subsystemid 0x17aa 0x21dd
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end
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device pci 1c.2 on # PCIe Port #3
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subsystemid 0x17aa 0x21dd
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end
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device pci 1c.3 on # PCIe Port #4
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subsystemid 0x17aa 0x21dd
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end
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device pci 1c.4 on # PCIe Port #5
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subsystemid 0x17aa 0x21dd
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end
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device pci 1c.5 on # PCIe Port #6
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subsystemid 0x17aa 0x21dd
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end
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device pci 1c.6 off # PCIe Port #7
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end
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device pci 1c.7 off # PCIe Port #8
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end
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device pci 1d.0 on # USB2 EHCI #1
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subsystemid 0x17aa 0x21dd
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end
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device pci 1e.0 off # PCI bridge
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end
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device pci 1f.0 on # LPC bridge PCI-LPC bridge
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subsystemid 0x17aa 0x21dd
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chip ec/lenovo/pmh7
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register "backlight_enable" = "0x01"
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register "dock_event_enable" = "0x01"
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device pnp ff.1 on # dummy
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end
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end
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chip ec/lenovo/h8
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register "config0" = "0xa7"
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register "config1" = "0x09"
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register "config2" = "0xa0"
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register "config3" = "0xc2"
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register "beepmask0" = "0x00"
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register "beepmask1" = "0x86"
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register "has_power_management_beeps" = "0"
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register "event2_enable" = "0xff"
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register "event3_enable" = "0xff"
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register "event4_enable" = "0xff"
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register "event5_enable" = "0xff"
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register "event6_enable" = "0xff"
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register "event7_enable" = "0xff"
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register "event8_enable" = "0xff"
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register "event9_enable" = "0xff"
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register "eventa_enable" = "0xff"
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register "eventb_enable" = "0xff"
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register "eventc_enable" = "0xff"
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register "eventd_enable" = "0xff"
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register "evente_enable" = "0xff"
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device pnp ff.2 on # dummy
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io 0x60 = 0x62
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io 0x62 = 0x66
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io 0x64 = 0x1600
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io 0x66 = 0x1604
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end
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end
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end
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device pci 1f.2 on # SATA Controller 1
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subsystemid 0x17aa 0x21dd
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end
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device pci 1f.3 on # SMBus
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subsystemid 0x17aa 0x21dd
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chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip
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device i2c 54 on
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end
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device i2c 55 on
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end
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device i2c 56 on
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end
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device i2c 57 on
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end
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device i2c 5c on
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end
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device i2c 5d on
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end
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device i2c 5e on
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end
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device i2c 5f on
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end
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end
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end
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device pci 1f.5 off # SATA Controller 2
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end
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device pci 1f.6 off # Thermal
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end
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end
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end
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end
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