66fe0c43be
This patch makes SOC files to use common/block/cpu/cpulib.c file's helper functions. Change-Id: I529c67cf20253cf819d1c13849300788104b083c Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19827 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
59 lines
1.7 KiB
C
59 lines
1.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corp.
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/cpu.h>
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#include <assert.h>
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#include <cpu/x86/msr.h>
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#include <intelblocks/msr.h>
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#include <program_loading.h>
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/*
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* This file supports the necessary hoops one needs to jump through since
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* early FSP component and early stages are running from cache-as-ram.
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*/
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static void flush_l1d_to_l2(void)
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{
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msr_t msr = rdmsr(MSR_POWER_MISC);
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msr.lo |= FLUSH_DL1_L2;
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wrmsr(MSR_POWER_MISC, msr);
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}
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static inline int is_car_addr(uintptr_t addr)
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{
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return ((addr >= CONFIG_DCACHE_RAM_BASE) &&
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(addr < (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)));
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}
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void platform_segment_loaded(uintptr_t start, size_t size, int flags)
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{
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/* Bail out if this is not the final segment. */
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if (!(flags & SEG_FINAL))
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return;
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char start_car_check = is_car_addr(start);
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char end_car_check = is_car_addr(start + size - 1);
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/* Bail out if loaded program segment does not lie in CAR region. */
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if (!start_car_check && !end_car_check)
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return;
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/* Loaded program segment should lie entirely within CAR region. */
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assert(start_car_check && end_car_check);
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flush_l1d_to_l2();
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}
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