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Maxim Polyakov 2bb3e78066 mb/ocp/tiogapass: rework GPIOs configuration using macros 
This format of PCH GPIOs configuration, unlike the raw DW0 and DW1
registers values from the inteltool dump, is more understandable and
makes the code much cleaner. The gpio.h file with PAD_CFG macros was
automatically generated using the util/intelp2m [1] utility:

./intelp2m -p lbg -file tiogapass/vendorbios/inteltool_gpio.log

According to the documentation [2], the Host Software Pad Ownership
register only affects the pads that are configured as input (GPI).
The intelp2m utility takes this into account when converting macros
and ignores bits from this register for the corresponding pads.

[1] https://review.coreboot.org/c/coreboot/+/35643
[2] Intel Document Number: 549921

Change-Id: I21e98721e58b00be9196927837daa2b5d2560822
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40731
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 		2020-05-01 21:58:15 +00:00
3rdparty Update vboot submodule to upstream master 2020-05-01 06:27:49 +00:00
Documentation documentation: Add documentation ideas for season of docs 2020-05-01 13:47:06 +00:00
LICENSES LICENSES: Add licenses used in the coreboot repo 2019-10-30 08:23:51 +00:00
configs configs/config.facebook_fbg1701: Rename file 2020-04-22 13:48:40 +00:00
payloads libpayload: Fix 16-bit read/write to PCI_COMMAND register 2020-05-01 06:26:38 +00:00
src mb/ocp/tiogapass: rework GPIOs configuration using macros 2020-05-01 21:58:15 +00:00
tests tests: Add device/i2c-test test case 2020-05-01 06:33:49 +00:00
util util/intelmetool: Fix 16-bit read/write PCI_COMMAND register 2020-05-01 06:18:46 +00:00
.checkpatch.conf
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.clang-format
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.editorconfig
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.gitignore cbfstool: Build vboot library 2020-03-23 08:34:23 +00:00
.gitmodules submodules: Add 3rdparty/amd_blobs 2019-10-31 12:28:38 +00:00
.gitreview
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AUTHORS AUTHORS: Add authors from util/ 2020-03-18 18:22:37 +00:00
COPYING
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MAINTAINERS MAINTAINERS: Update GA-H61M-S2PV 2020-04-16 17:02:28 +00:00
Makefile tests: Add build subsystem for unit testing coreboot 2020-05-01 06:32:47 +00:00
Makefile.inc Makefile: Set FMAP size to 0x200 for non-x86 boards with default fmd 2020-04-20 06:07:08 +00:00
README.md README.md: Remove link to deprecated wiki 2019-11-16 20:39:55 +00:00
gnat.adc
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toolchain.inc Makefile: Remove romcc 2019-12-27 08:59:59 +00:00

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.