Harshit Sharma 2bcaba0fd4 lib: Add ASan stub ... Add a Kconfig option to enable address sanitizer on x86 architecture. Create ASan dummy functions. And add relevant gcc flags to compile ramstage with ASan. Change-Id: I6d87e48b6786f02dd46ea74e702f294082fd8891 Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>		2020-08-21 07:35:07 +00:00
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acpi	soc/amd/acpi: Move ACPI IVRS generation to coreboot	2020-08-20 19:42:05 +00:00
arch	arch/x86/boot: Jump to payload in protected mode	2020-08-19 09:06:43 +00:00
commonlib	src: Remove unused 'include <stdint.h>	2020-07-14 16:11:10 +00:00
console	src: Remove unused 'include <stddef.h>	2020-08-18 12:15:44 +00:00
cpu	mb/emulation/qemu-q35,qemu-i440fx: Add x86_64 support	2020-08-19 10:50:49 +00:00
device	{sb/intel/*/azalia.c,device/azalia_device.c}: Reduce differences	2020-08-17 06:58:45 +00:00
drivers	drivers/spi/tpm: Enable long cr50 ready pulses for Tiger Lake systems	2020-08-20 19:34:46 +00:00
ec	ec/google/chromeec: Add helper to request AP reset	2020-08-14 08:35:15 +00:00
include	soc/amd/acpi: Move ACPI IVRS generation to coreboot	2020-08-20 19:42:05 +00:00
lib	lib: Add ASan stub	2020-08-21 07:35:07 +00:00
mainboard	mb/google/asurada: Fixup BOOT_DEVICE_SPI_FLASH_BUS default value	2020-08-21 05:59:42 +00:00
northbridge	src: Remove unused 'include <delay.h>'	2020-08-18 12:19:18 +00:00
security	drivers/spi/tpm: Enable long cr50 ready pulses for Tiger Lake systems	2020-08-20 19:34:46 +00:00
soc	cse_lite: Move global reset after MRC writeback	2020-08-20 23:01:49 +00:00
southbridge	sb/intel/lynxpoint: Drop unneeded and rotten Kconfig option	2020-08-20 08:56:21 +00:00
superio	src: Remove unused 'include <delay.h>'	2020-08-18 12:19:18 +00:00
vendorcode	vc/amd/agesa/f16kb: raise the UDIMM Freq limit 1333MT/s values to 1600MT/s	2020-08-20 08:54:41 +00:00
Kconfig	lib: Add ASan stub	2020-08-21 07:35:07 +00:00