coreboot-kgpe-d16/src/soc/intel
Aaron Durbin 2b3e0cdfc4 soc/intel/common/lpss_i2c: configure buses by rise/fall times
The default register count calculations are leading to higher
frequencies than expected. Provide an alternative method for
calculating the register counts by utilizing the rise and
fall times of the bus. If the rise time is supplied the
rise/fall time values are used, but the register overrides
take precedence over the rise/fall time calculation.  This
allows platforms to choose whichever method works the best.

BUG=chrome-os-partner:58889

Change-Id: I7747613ce51d8151848acd916c09ae97bfc4b86a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17350
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-11-12 00:19:22 +01:00
..
apollolake soc/intel/common/lpss_i2c: configure buses by rise/fall times 2016-11-12 00:19:22 +01:00
baytrail intel car: Remove references to DCACHE_RAM_ROMSTACK_SIZE 2016-11-08 19:16:24 +01:00
braswell intel car: Remove references to DCACHE_RAM_ROMSTACK_SIZE 2016-11-08 19:16:24 +01:00
broadwell intel car: Remove references to DCACHE_RAM_ROMSTACK_SIZE 2016-11-08 19:16:24 +01:00
common soc/intel/common/lpss_i2c: configure buses by rise/fall times 2016-11-12 00:19:22 +01:00
fsp_baytrail fsp_baytrail: Refactor code for SPI debug messages 2016-09-06 21:17:59 +02:00
fsp_broadwell_de soc/intel/fsp_broadwell_de: Fix system hang when timestamp is enabled 2016-10-09 19:08:07 +02:00
quark soc/intel/quark: Fix FSP 2.0 build 2016-09-30 01:16:51 +02:00
sch src/soc: Remove unnecessary whitespace before "\n" and "\t" 2016-08-28 18:25:14 +02:00
skylake soc/intel/common/lpss_i2c: configure buses by rise/fall times 2016-11-12 00:19:22 +01:00