coreboot-kgpe-d16/src/cpu/intel/model_2065x
Kyösti Mälkki bbf013c38f nehalem/sandy/ivy/haswell: Enable WRPROT cache for all of flash
CBFS could start from below 4MB, and should be cacheable for the
purpose of early microcode update and CBFS search for romstage file.

Change-Id: Ia2a1c6e5fdcc3201fafc8cf5c841cebbbf0b30c9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4626
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-15 15:27:33 +01:00
..
acpi.c Rename SANDYBRIDGE_BCLK to NEHALEM_BCLK in 2065x. 2013-11-23 14:32:29 +01:00
bootblock.c nehalem/sandy/ivy/haswell: Enable WRPROT cache for all of flash 2014-01-15 15:27:33 +01:00
cache_as_ram.inc Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR 2014-01-15 15:26:48 +01:00
chip.h Add support for Intel Nehalem CPU 2013-06-13 00:32:01 +02:00
finalize.c Add support for Intel Nehalem CPU 2013-06-13 00:32:01 +02:00
Kconfig cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS 2013-12-13 01:28:36 +01:00
Makefile.inc intel/2065x: Use TSC for udelay() 2013-11-13 00:38:45 +01:00
microcode-m9220655_00000003.h Add support for Intel Nehalem CPU 2013-06-13 00:32:01 +02:00
microcode_blob.c Add support for Intel Nehalem CPU 2013-06-13 00:32:01 +02:00
microcode_blob.h Add support for Intel Nehalem CPU 2013-06-13 00:32:01 +02:00
model_2065x.h Rename SANDYBRIDGE_BCLK to NEHALEM_BCLK in 2065x. 2013-11-23 14:32:29 +01:00
model_2065x_init.c Rename SANDYBRIDGE_BCLK to NEHALEM_BCLK in 2065x. 2013-11-23 14:32:29 +01:00
tsc_freq.c Rename SANDYBRIDGE_BCLK to NEHALEM_BCLK in 2065x. 2013-11-23 14:32:29 +01:00